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GS84018CGT-250I PDF预览

GS84018CGT-250I

更新时间： 2024-11-26 19:00:07
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
22页 408K
描述
Cache SRAM, 256KX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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GS84018CGT-250I 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LQFP,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.B风险等级：5.66
最长访问时间：5.5 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100长度：20 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Pure Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS84018CGT-250I 数据手册

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GS84018/32/36CGT-250/200/166/150  
TQFP  
Commercial Temp  
Industrial Temp  
250 MHz–150 MHz  
256K x 18, 128K x 32, 128K x 36  
4Mb Sync Burst SRAMs  
3.3 V V  
DD  
3.3 V and 2.5 V I/O  
counter may be configured to count in either linear or  
Features  
interleave order with the Linear Burst Order (LBO) input. The  
burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
• FT pin for user-configurable flow through or pipelined  
operation  
• Single Cycle Deselect (SCD) operation  
• 3.3 V +10%/–5% core power supply  
Flow Through/Pipeline Reads  
• 2.5 V or 3.3 V I/O supply  
The function of the Data Output register can be controlled by  
the user via the FT mode pin/bump (pin 14 in the TQFP and  
bump 5R in the BGA). Holding the FT mode pin/bump low  
places the RAM in Flow Through mode, causing output data to  
bypass the Data Output Register. Holding FT high places the  
RAM in Pipelined mode, activating the rising-edge-triggered  
Data Output Register.  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipelined mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Common data inputs and data outputs  
• Clock control, registered, address, data, and control  
• Internal self-timed write cycle  
SCD Pipelined Reads  
• Automatic power-down for portable applications  
• RoHS-compliant 100-lead TQFP package  
The GS84018/32/36CGT is an SCD (Single Cycle Deselect)  
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)  
versions are also available. SCD SRAMs pipeline deselect  
commands one stage less than read commands. SCD RAMs  
begin turning off their outputs immediately after the deselect  
command has been captured in the input registers.  
Functional Description  
Applications  
The GS84018/32/36CGT is a 4,718,592-bit (4,194,304-bit for  
x32 version) high performance synchronous SRAM with a 2-  
bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications ranging from DSP main store  
to networking chip set support. The GS84018/32/36CGT is  
available in a JEDEC standard 100-lead TQFP package.  
Byte Write and Global Write  
Byte write operation is performed by using byte write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Sleep Mode  
Controls  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
Core and Interface Voltages  
The GS84018/32/36CGT operates on a 3.3 V power supply  
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.  
Separate output power (V  
) pins are used to de-couple  
DDQ  
output noise from the internal circuit.  
Parameter Synopsis  
-250  
-200  
-166  
-150  
Unit  
tKQ  
2.5  
4.0  
3.0  
5.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x32/x36)  
195  
225  
170  
195  
160  
185  
140  
160  
mA  
mA  
tKQ  
5.5  
5.5  
6.5  
6.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
160  
180  
140  
160  
135  
155  
128  
145  
mA  
mA  
Rev: 1.01 11/2014  
1/22  
© 2014, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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GS84018GB-166I GSI

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 		Cache SRAM, 256KX18, 8.5ns, CMOS, PBGA119, BGA-119
GS84018GB-166IT GSI

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 		Cache SRAM, 256KX18, 8.5ns, CMOS, PBGA119, BGA-119
GS84018GB-166T GSI

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 		Cache SRAM, 256KX18, 8.5ns, CMOS, PBGA119, BGA-119
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 		Cache SRAM, 256KX18, 12ns, CMOS, PQFP100, TQFP-100
GS84018GT-166IT GSI

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 		Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, TQFP-100

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