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GS84018B-100 PDF预览

GS84018B-100

更新时间： 2024-11-19 04:19:55
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
31页 629K
描述
256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs

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GS84018B-100 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA, BGA119,7X17,50
针数：119Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.72最长访问时间：12 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：119
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.19 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS84018B-100 数据手册

 浏览型号GS84018B-100的Datasheet PDF文件第2页浏览型号GS84018B-100的Datasheet PDF文件第3页浏览型号GS84018B-100的Datasheet PDF文件第4页浏览型号GS84018B-100的Datasheet PDF文件第5页浏览型号GS84018B-100的Datasheet PDF文件第6页浏览型号GS84018B-100的Datasheet PDF文件第7页 
GS84018/32/36T/B-180/166/150/100  
180Mhz - 100Mhz  
TQFP, BGA  
Commercial Temp  
Industrial Temp  
256K x 18, 128K x 32, 128K x 36  
3.3V VDD  
4Mb Sync Burst SRAMs  
3.3V & 2.5V I/O  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• FT pin for user configurable flow through or pipelined operation.  
• Single Cycle Deselect (SCD) Operation.  
Flow Through / Pipeline Reads  
The function of the Data Output register can be controlled by the user  
via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the  
BGA, ) . Holding the FT mode pin/bump low places the RAM in Flow  
through mode, causing output data to bypass the Data Output  
Register. Holding FT high places the RAM in Pipelined Mode,  
activating the rising edge triggered Data Output Register.  
• 3.3V +10%/-5% Core power supply  
• 2.5V or 3.3V I/O supply.  
• LBO pin for linear or interleaved burst mode.  
• Internal input resistors on mode pins allow floating mode pins.  
• Default to Interleaved Pipelined Mode.  
• Byte write (BW) and/or global write (GW) operation.  
• Common data inputs and data outputs.  
• Clock Control, registered, address, data, and control.  
• Internal Self-Timed Write cycle.  
• Automatic power-down for portable applications.  
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.  
SCD Pipelined Reads  
The GS84018/32/36 is an SCD (Single Cycle Deselect) pipelined  
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also  
available.SCD SRAMs pipeline deselect commands one stage less  
than read commands. SCD RAMs begin turning off their outputs  
immediately after the deselect command has been captured in the  
input registers.  
-180  
-166  
-150  
-100  
tCycle 5.5ns  
6.0ns  
3.5ns  
6.6ns  
3.8ns  
10ns  
4.5ns  
Byte Write and Global Write  
Pipeline  
3-1-1-1  
tKQ  
IDD  
3.2ns  
Byte write operation is performed by using byte write enable (BW)  
input combined with one or more individual byte write signals (Bx). In  
addition, Global Write (GW) is available for writing all bytes at one  
time, regardless of the Byte Write control inputs.  
330mA 310mA 275mA 190mA  
tKQ  
tCycle  
IDD  
8ns  
10ns  
8.5ns  
10ns  
10ns  
10ns  
12ns  
15ns  
Flow Through  
2-1-1-1  
190mA 190mA 190mA 140mA  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion (High) of  
the ZZ signal, or by stopping the clock (CK). Memory data is retained  
during Sleep mode.  
Functional Description  
Core and Interface Voltages  
Applications  
The GS84018/32/36 operates on a 3.3V power supply and all inputs/  
outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)  
pins are used to de-couple output noise from the internal circuit.  
The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version)  
high performance synchronous SRAM with a 2 bit burst address  
counter. Although of a type originally developed for Level 2 Cache  
applications supporting high performance CPU’s, the device now  
finds application in synchronous SRAM applications ranging from  
DSP main store to networking chip set support. The GS84018/32/36  
is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA  
package.  
Controls  
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control  
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are  
synchronous and are controlled by a positive edge triggered clock  
input (CK). Output enable (G) and power down control (ZZ) are  
asynchronous inputs. Burst cycles can be initiated with either ADSP  
or ADSC inputs. In Burst mode, subsequent burst addresses are  
generated internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or interleave order  
with the Linear Burst Order (LBO) input. The Burst function need not  
Rev: 2.05 6/2000  
1/31  
© 1999, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...31

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