Datasheet > GS832218B-150IVT

GS832218B-150IVT

更新时间： 2024-11-19 20:46:55

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
42页	2057K
描述
Cache SRAM, 2MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119

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GS832218B-150IVT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA,	针数：	119
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.1
最长访问时间：	8.5 ns	其他特性：	FLOW-THROUGH OR PIELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
长度：	22 mm	内存密度：	37748736 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
功能数量：	1	端子数量：	119
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.99 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GS832218B-150IVT 数据手册

GS832218/36/72(B/E/C)-xxxV

119-, 165-, & 209-Pin BGA

Commercial Temp

Industrial Temp

250 MHz–133 MHz

2M x 18, 1M x 36, 512K x 72

36Mb S/DCD Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-, 165-, and 209-bump BGA package

• RoHS-compliant packages available

SCD and DCD Pipelined Reads

The GS832218/36/72-xxxV is a SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Functional Description

Applications

The GS832218/36/72-xxxV is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

FLXDrive™

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS832218/36/72-xxxV operates on a 1.8 V or 2.5 V power

supply. All inputs are 1.8 V or 2.5 V compatible. Separate output

power (V_DDQ) pins are used to decouple output noise from the

internal circuits and are 1.8 V or 2.5 V compatible.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

t_KQ

3.0

4.0

3.0

4.4

3.0

5.0

3.5

6.0

3.8

6.7

4.0

7.5

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x36)

Curr (x72)

285

350

440

265

320

410

245

295

370

220

260

320

210 185

240 215

300 265

t_KQ

6.5

7.0

7.5

8.0

8.5

tCycle

Flow

Through

2-1-1-1

Curr (x18)

Curr (x36)

Curr (x72)

205

235

315

195

225

295

185

210

265

175

200

255

165 155

190 175

240 230

Rev: 1.07 9/2008

1/42

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...42

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与GS832218B-150IVT相关器件

型号	品牌	获取价格	描述	数据表
GS832218B-150V	GSI	获取价格	Cache SRAM, 2MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832218B-166	GSI	获取价格	Cache SRAM, 2MX18, 8ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
GS832218B-166I	ETC	获取价格	2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832218B-166IT	GSI	获取价格	Cache SRAM, 2MX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FBGA-119
GS832218B-166V	GSI	获取价格	Cache SRAM, 2MX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832218B-166VT	GSI	获取价格	Cache SRAM, 2MX18, 8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832218B-200	GSI	获取价格	Cache SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
GS832218B-200I	GSI	获取价格	Cache SRAM, 2MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FBGA-119
GS832218B-200V	GSI	获取价格	Cache SRAM, 2MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119
GS832218B-200VT	GSI	获取价格	Cache SRAM, 2MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FPBGA-119

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