Datasheet > GS8321Z18AD-400I

GS8321Z18AD-400I

更新时间： 2024-11-06 14:57:07

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
34页	500K
描述
165 BGA

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GS8321Z18AD-400I 数据手册

GS8321Z18/32/36AD-400/375/333/250/200/150

400 MHz–150 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

36Mb Pipelined and Flow Through

Synchronous NBT SRAM

2.5 V, or 3.3 V V

2.5 V, or 3.3 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

• Fully pin-compatible with both pipelined and flow through

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V, or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 165-bump BGA package

• RoHS-compliant 165-bump BGA package available

The GS8321Z18/32/36AD may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

Functional Description

The GS8321Z18/32/36AD is a 36Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8321Z18/32/36AD is implemented with GSI's high

performance CMOS technology and is available in JEDEC-

standard 165-bump BGA package.

Parameter Synopsis

-400

-375

-333

-250

-200

-150

Unit

2.5

2.66

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

395

475

390

455

355

415

280

335

240

280

205

230

4.0

4.2

4.5

5.5

6.5

7.5

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

290

335

275

320

260

305

235

270

200

240

190

220

Rev: 1.03 8/2013

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...34

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与GS8321Z18AD-400I相关器件

型号	品牌	获取价格	描述	数据表
GS8321Z18AGD-150	GSI	获取价格	165 BGA
GS8321Z18AGD-150I	GSI	获取价格	165 BGA
GS8321Z18AGD-150IV	GSI	获取价格	165 BGA
GS8321Z18AGD-150V	GSI	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8321Z18AGD-200	GSI	获取价格	165 BGA
GS8321Z18AGD-200I	GSI	获取价格	165 BGA
GS8321Z18AGD-200IV	GSI	获取价格	ZBT SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8321Z18AGD-200IVT	GSI	获取价格	ZBT SRAM, 2MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8321Z18AGD-200V	GSI	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8321Z18AGD-250	GSI	获取价格	165 BGA

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