GS81280Z18/36RT-333M/250M
GS8640Z18/36RT-333M/250M
GS8320Z18/36RT-333M/250M
333 MHz–250 MHz
Rad-Tolerant SRAM
144Mb/72Mb/36Mb PL/FT No Bus Turnaround SRAMs
100-Pin TQFP
Military Temp
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
SRAMs, allow utilization of all available bus bandwidth by
eliminating the need to insert deselect cycles when the device
is switched from read to write cycles.
Features
• Aerospace-Level Product
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb
devices
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
The GS81280Z18/36RT, GS8640Z18/36RT, and
GS8320Z18/36RT may be configured by the user to operate in
Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
• 100-pin TQFP package
Radiation Performance
• Total Ionizing Dose (TID) > 50krads(Si)
• Destructive Single Event Latchup Immunity >37 MeV.cm2/mg
(100C)
Functional Description
The GS81280Z18/36RT, GS8640Z18/36RT, and
GS8320Z18/36RT are Synchronous Static SRAMs. GSI's NBT
SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/
double late write or flow through read/single late write
The GS81280Z18/36RT, GS8640Z18/36RT, and
GS8320Z18/36RT are implemented with GSI's high
performance CMOS technology and are available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-333M -250M
Unit
tKQ
2.5
3.0
2.5
4.0
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x32/x36)
530
600
430
470
mA
mA
tKQ
tCycle
4.5
4.5
5.5
5.5
ns
ns
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
400
435
360
380
mA
mA
Rev: 1.01a 10/2020
1/25
© 2018, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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