Datasheet > 存储 > SRAM> GS8320Z18GT-133IV

GS8320Z18GT-133IV

更新时间： 2024-11-09 03:11:43

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
23页	1086K
描述
36Mb Pipelined and Flow Through Synchronous NBT SRAMs

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Preliminary

GS8320Z18/36T-xxxV

250 MHz–133 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

36Mb Pipelined and Flow Through

Synchronous NBT SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

The GS8320Z18/36T-xxxV may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

Functional Description

The GS8320Z18/36T-xxxV is a 36Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8320Z18/36T-xxxV is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

3.0 3.0 3.0 3.5 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.6 7.5 ns

Pipeline

3-1-1-1

tCycle

Curr (x18) 285 265 245 220 210 185 mA

Curr (x32/x36) 350 320 295 260 240 215 mA

6.5 7.0 7.5 8.0 8.5 8.5 ns

Flow

Through

2-1-1-1

tCycle

Curr (x18) 205 195 185 175 165 155 mA

Curr (x32/x36) 235 225 210 200 190 175 mA

Rev: 1.02 5/2006

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...23

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与GS8320Z18GT-133IV相关器件

型号	品牌	获取价格	描述	数据表
GS8320Z18GT-133T	ETC	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8320Z18GT-133V	GSI	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18GT-133VT	GSI	获取价格	暂无描述
GS8320Z18GT-150	GSI	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18GT-150I	GSI	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18GT-150IT	ETC	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8320Z18GT-150IV	GSI	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18GT-150T	ETC	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8320Z18GT-150V	GSI	获取价格	36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18GT-150VT	GSI	获取价格	暂无描述

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