Datasheet > 存储 > SRAM> GS832036T-150T

GS832036T-150T

更新时间： 2024-11-19 13:07:59

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
25页	645K
描述
Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, TQFP-100

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技术参数
数据手册

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GS832036T-150T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.77	最长访问时间：	8.5 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY	最大时钟频率 (fCLK)：	150 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	37748736 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5/3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.06 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.17 mA
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS832036T-150T 数据手册

Preliminary

GS832018/32/36T-250/225/200/166/150/133

250 MHz–133 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Byte Write and Global Write

Functional Description

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS832018/32/36T is a 37,748,736-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Core and Interface Voltages

The GS832018/32/36T operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

2.5 2.7 3.0 3.5 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.6 7.5 ns

Pipeline

3-1-1-1

tCycle

Curr (x18) 285 265 245 220 210 185 mA

Curr (x32/x36) 350 320 295 260 240 215 mA

6.5 7.0 7.5 8.0 8.5 8.5 ns

Flow

Through

2-1-1-1

tCycle

Curr (x18) 205 195 185 175 165 155 mA

Curr (x32/x36) 235 225 210 200 190 175 mA

Rev: 1.02 10/2004

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...25

中文翻译

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与GS832036T-150T相关器件

型号	品牌	获取价格	描述	数据表
GS832036T-150V	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832036T-150VT	GSI	获取价格	Cache SRAM, 1MX36, 8.5ns, CMOS, PQFP100, TQFP-100
GS832036T-166	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832036T-166I	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832036T-166IT	GSI	获取价格	Cache SRAM, 1MX36, 8ns, CMOS, PQFP100, TQFP-100
GS832036T-166IV	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832036T-166IVT	GSI	获取价格	Cache SRAM, 1MX36, 8ns, CMOS, PQFP100, TQFP-100
GS832036T-166V	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
GS832036T-166VT	GSI	获取价格	Cache SRAM, 1MX36, 8ns, CMOS, PQFP100, TQFP-100
GS832036T-200	GSI	获取价格	2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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