GS82612DT19/37CE/LE-350M/250M (S/Q/V)
GS81332DT19/37CE/LE-350M/250M (S/Q/V)
GS8692DT19/37CE/LE-350M/250M (S/Q/V)
350 MHz–250 MHz
Rad-Hard SRAM
288Mb/144Mb/72Mb Burst of 4 SigmaQuad-II+
165-Bump CCGA & LGA
Military Temp
1.8 V V
DD
TM
1.8 V and 1.5 V I/O
Features
SigmaQuad™ Family Overview
• Aerospace-Level Product
The GS82612DT19/37, GS81332DT19/37, and
• 2.0 clock Latency with DLL on
• 1.0 clock Latency with DLL off
GS8692DT19/37 are built in compliance with the SigmaQuad-
II+ SRAM pinout standard for Separate I/O synchronous
SRAMs. They are 301,989,888-bit (288Mb), 150,994,944-bit
(144Mb), and 75,497,472-bit (72Mb) SRAMs. These
SigmaQuad SRAMs are just one element in a family of low
power, low voltage HSTL I/O SRAMs designed to operate at
the speeds needed to implement economical high performance
networking systems.
• Optional DLL-controlled output timing
• Can be operated with DLL on or off
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
Clocking and Addressing Schemes
The Rad-Hard SigmaQuad-II+ SRAMs are synchronous
devices. They employ two input register clock inputs, K and K.
K and K are independent single-ended clock inputs, not
differential inputs to a single differential clock input buffer.
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump Ceramic Column Grid Array (CCGA) and
165-bump Land Grid Array (LGA) packages
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 18 has a
4M addressable index).
Radiation Performance
• Total Ionizing Dose (TID) > 100krads(Si)
• Single Event Latchup Immunity > 77.3 MeV.cm2/mg (125C)
Parameter Synopsis
-350M
-250M
4.0 ns
tKHKH
tKHQV
2.86 ns
0.45 ns
0.45 ns
Rev: 1.02a 9/2021
1/43
© 2018, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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