GS82583ET18/36GK-675/625/550/500
Up to 675 MHz
260-Pin BGA
Commercial Temp
Industrial Temp
288Mb SigmaDDR-IIIe™
Burst of 2 SRAM
1.3V V
DD
1.2V, 1.3V, or 1.5V V
DDQ
Features
Clocking and Addressing Schemes
• 8Mb x 36 and 16Mb x 18 organizations available
• 675 MHz maximum operating frequency
• 675 MT/s peak transaction rate (in millions per second)
• 48 Gb/s peak data bandwidth (in x36 devices)
• Common I/O DDR Data Bus
The GS82583ET18/36GK SigmaDDR-IIIe SRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 2 Read and Write operations
• 3 cycle Read Latency
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
• 1.3V nominal core voltage
• 1.2V, 1.3V, or 1.5V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
Each internal read and write operation in a SigmaDDR-IIIe B2
SRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 SRAM is always one address pin
less than the advertised index depth (e.g. the 16M x 18 has 8M
addressable index).
SigmaDDR-IIIe™ Family Overview
SigmaDDR-IIIe SRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
SRAMs. Although very similar to GSI's second generation of
networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),
these third generation devices offer several new features that
help enable significantly higher performance.
Parameter Synopsis
V
Speed Grade
Max Operating Frequency
Read Latency
DD
-675
-625
-550
-500
675 MHz
625 MHz
550 MHz
500 MHz
3 cycles
3 cycles
3 cycles
3 cycles
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
Rev: 1.07 12/2017
1/29
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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