Datasheet > GS8161Z36DT-333IVT

GS8161Z36DT-333IVT

更新时间： 2024-11-20 04:08:19

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
35页	488K
描述
ZBT SRAM, 512KX36, 5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GS8161Z36DT-333IVT 数据手册

浏览型号GS8161Z36DT-333IVT的Datasheet PDF文件第2页

浏览型号GS8161Z36DT-333IVT的Datasheet PDF文件第3页

浏览型号GS8161Z36DT-333IVT的Datasheet PDF文件第4页

浏览型号GS8161Z36DT-333IVT的Datasheet PDF文件第5页

浏览型号GS8161Z36DT-333IVT的Datasheet PDF文件第6页

浏览型号GS8161Z36DT-333IVT的Datasheet PDF文件第7页

Preliminary

GS8161ZxxD(GT/D)-xxxV

333 MHz–150 MHz

1.8 V or 2.5 V V_DD

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

• Fully pin-compatible with both pipelined and flow through

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and

144Mb devices

The GS8161ZxxD(GT/D)-xxxV may be configured by the user

to operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 165-bump BGA package

• RoHS-compliant 100-pin TQFP and BGA packages available

Functional Description

The GS8161ZxxD(GT/D)-xxxV is an 18Mbit Synchronous

Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL

or other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8161ZxxD(GT/D)-xxxV is implemented with GSI's

high performance CMOS technology and is available in

JEDEC-standard 165-bump FP-BGA package.

Parameter Synopsis

-333

-250

-200

-150

Unit

3.0

4.0

3.0

5.0

3.8

6.7

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x36)

TBD

5.0

5.5

6.5

7.5

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x36)

TBD

Rev: 1.00 6/2011

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

中文翻译

下载PDF

与GS8161Z36DT-333IVT相关器件

型号	品牌	获取价格	描述	数据表
GS8161Z36DT-333V	GSI	获取价格	ZBT SRAM, 512KX36, 5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-333VT	GSI	获取价格	ZBT SRAM, 512KX36, 5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-375IT	GSI	获取价格	ZBT SRAM, 512KX36, 4.2ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-375T	GSI	获取价格	ZBT SRAM, 512KX36, 4.2ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-400I	GSI	获取价格	ZBT SRAM, 512KX36, 4ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36DT-400IT	GSI	获取价格	ZBT SRAM, 512KX36, 4ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS8161Z36GD-133IT	GSI	获取价格	ZBT SRAM, 512KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161Z36GD-133T	GSI	获取价格	ZBT SRAM, 512KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161Z36GD-150T	GSI	获取价格	ZBT SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS8161Z36GD-166I	GSI	获取价格	ZBT SRAM, 512KX36, 7ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

与GS8161Z36DT-333IVT相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

45

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8161Z36DT-333IVT

GS8161Z36DT-333IVT 数据手册

与GS8161Z36DT-333IVT相关器件

与GS8161Z36DT-333IVT相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8161Z36DT-333IVT

GS8161Z36DT-333IVT 数据手册

与GS8161Z36DT-333IVT相关器件

与GS8161Z36DT-333IVT相关文章

您还可以找

您在本页遇到什么问题？