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GS8161E36BD-250VT PDF预览

GS8161E36BD-250VT

更新时间： 2024-10-27 12:59:27
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
35页 1504K
描述
Cache SRAM, 512KX36, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165

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GS8161E36BD-250VT 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1 MM PITCH, FPBGA-165针数：165
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.71
Is Samacsys：N最长访问时间：5.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 2.5V SUPPLYJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

GS8161E36BD-250VT 数据手册

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GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
250 MHz–150 MHz  
1M x 18, 512K x 36, 512K x 36  
18Mb Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline operation  
• Dual Cycle Deselect (DCD) operation  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP and 165-bump BGA packages  
available  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
DCD Pipelined Reads  
The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
is a DCD (Dual Cycle Deselect) pipelined synchronous  
SRAM. SCD (Single Cycle Deselect) versions are also  
available. DCD SRAMs pipeline disable commands to the  
same degree as read commands. DCD RAMs hold the deselect  
command for one full cycle and then begin turning off their  
outputs just after the second rising edge of clock.  
Functional Description  
Applications  
The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
is a 18,874,368-bit high performance synchronous SRAM with  
a 2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Controls  
Sleep Mode  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,  
BW, GW) are synchronous and are controlled by a positive-  
edge-triggered clock input (CK). Output enable (G) and power  
down control (ZZ) are asynchronous inputs. Burst cycles can  
be initiated with either ADSP or ADSC inputs. In Burst mode,  
subsequent burst addresses are generated internally and are  
controlled by ADV. The burst address counter may be  
configured to count in either linear or interleave order with the  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V  
and 2.5 V compatible. Separate output power (V  
) pins are  
DDQ  
used to decouple output noise from the internal circuits and are  
3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-250  
-200  
-150  
Unit  
tKQ  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
295  
345  
245  
285  
200  
225  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
tKQ  
tCycle  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
Flow Through  
2-1-1-1  
225  
255  
200  
220  
185  
205  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Rev: 1.03 9/2005  
1/35  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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GS8161E36BD-300I GSI

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GS8161E36BGD-150 GSI

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 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E36BGD-150I GSI

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GS8161E36BGD-150IV GSI

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 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E36BGD-150IVT GSI

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 		Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-1
GS8161E36BGD-150T GSI

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 		暂无描述
GS8161E36BGD-150V GSI

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 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E36BGD-150VT GSI

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 		Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-1

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