5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> GS8161E18BGD-250
GS8161E18BGD-250 PDF预览

GS8161E18BGD-250

更新时间： 2024-11-20 05:10:43
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
35页 1504K
描述
1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs

阅读下载

中文翻译

获取价格

GS8161E18BGD-250 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：165
Reach Compliance Code：unknownECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.64
Is Samacsys：N最长访问时间：5.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLYJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX18
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.4 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

GS8161E18BGD-250 数据手册

 浏览型号GS8161E18BGD-250的Datasheet PDF文件第2页浏览型号GS8161E18BGD-250的Datasheet PDF文件第3页浏览型号GS8161E18BGD-250的Datasheet PDF文件第4页浏览型号GS8161E18BGD-250的Datasheet PDF文件第5页浏览型号GS8161E18BGD-250的Datasheet PDF文件第6页浏览型号GS8161E18BGD-250的Datasheet PDF文件第7页 
GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
100-Pin TQFP & 165-Bump BGA  
Commercial Temp  
Industrial Temp  
250 MHz–150 MHz  
1M x 18, 512K x 36, 512K x 36  
18Mb Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Features  
• FT pin for user-configurable flow through or pipeline operation  
• Dual Cycle Deselect (DCD) operation  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP and 165-bump BGA packages  
available  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin (Pin 14). Holding the FT mode  
pin low places the RAM in Flow Through mode, causing  
output data to bypass the Data Output Register. Holding FT  
high places the RAM in Pipeline mode, activating the rising-  
edge-triggered Data Output Register.  
DCD Pipelined Reads  
The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
is a DCD (Dual Cycle Deselect) pipelined synchronous  
SRAM. SCD (Single Cycle Deselect) versions are also  
available. DCD SRAMs pipeline disable commands to the  
same degree as read commands. DCD RAMs hold the deselect  
command for one full cycle and then begin turning off their  
outputs just after the second rising edge of clock.  
Functional Description  
Applications  
The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
is a 18,874,368-bit high performance synchronous SRAM with  
a 2-bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Controls  
Sleep Mode  
Addresses, data I/Os, chip enable (E1), address burst control  
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,  
BW, GW) are synchronous and are controlled by a positive-  
edge-triggered clock input (CK). Output enable (G) and power  
down control (ZZ) are asynchronous inputs. Burst cycles can  
be initiated with either ADSP or ADSC inputs. In Burst mode,  
subsequent burst addresses are generated internally and are  
controlled by ADV. The burst address counter may be  
configured to count in either linear or interleave order with the  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Core and Interface Voltages  
The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)  
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V  
and 2.5 V compatible. Separate output power (V  
) pins are  
DDQ  
used to decouple output noise from the internal circuits and are  
3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-250  
-200  
-150  
Unit  
tKQ  
2.5  
4.0  
3.0  
5.0  
3.8  
6.7  
ns  
ns  
tCycle  
Pipeline  
3-1-1-1  
295  
345  
245  
285  
200  
225  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
tKQ  
tCycle  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
Flow Through  
2-1-1-1  
225  
255  
200  
220  
185  
205  
mA  
mA  
Curr (x18)  
Curr (x32/x36)  
Rev: 1.03 9/2005  
1/35  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...35

中文翻译

下载PDF

与GS8161E18BGD-250相关器件

型号 品牌 获取价格 描述 数据表
GS8161E18BGD-250I GSI

获取价格

 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-250IV GSI

获取价格

 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-250IVT GSI

获取价格

 		Cache SRAM, 1MX18, 5.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
GS8161E18BGD-250V GSI

获取价格

 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-250VT GSI

获取价格

 		暂无描述
GS8161E18BGD-300T GSI

获取价格

 		Cache SRAM, 1MX18, 5.3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, LEAD FREE, FBGA-165
GS8161E18BGT-150 GSI

获取价格

 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-150I GSI

获取价格

 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-150IV GSI

获取价格

 		1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGT-150IVT GSI

获取价格

 		Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

与GS8161E18BGD-250相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证