Datasheet > 存储 > SRAM> GS8160V32AT-300I

GS8160V32AT-300I

更新时间： 2024-11-07 05:10:43

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器
页数	文件大小	规格书
24页	490K
描述
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

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技术参数
数据手册

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GS8160V32AT-300I 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	最长访问时间：	5 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	16777216 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	2 V
最小供电电压 (Vsup)：	1.6 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GS8160V32AT-300I 数据手册

Preliminary

GS8160V18/32/36AT-350/333/300/250/200/150

350 MHz–150 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

1M x 18, 512K x 32, 512K x 36

1.8 V V_DD

1.8 V I/O

18Mb Sync Burst SRAMs

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 1.8 V +10%/–10% core power supply

• 1.8 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode pin

low places the RAM in Flow Through mode, causing output

data to bypass the Data Output Register. Holding FT high

places the RAM in Pipeline mode, activating the rising-edge-

triggered Data Output Register.

Byte Write and Global Write

Functional Description

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS8160V18/32/36AT is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8160V18/32/36AT operates on a 1.8 V power supply.

All input are 1.8 V compatible. Separate output power (V

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

)

DDQ

pins are used to decouple output noise from the internal circuits

and are 1.8 V compatible.

Parameter Synopsis

-350 -333 -300 -250 -200 -150 Unit

t_KQ

1.8

2.85

2.0

3.0

2.2

3.3

2.3

4.0

2.7

5.0

3.3

6.7

tCycle

Pipeline

3-1-1-1

395

455

370

430

335

390

280

330

230

270

185

210

Curr (x18)

Curr (x32/x36)

t_KQ

tCycle

4.5

4.7

5.0

5.5

6.5

7.5

Flow

Through

2-1-1-1

270

305

250

285

230

270

210

240

185

205

170

190

Curr (x18)

Curr (x32/x36)

Rev: 1.00a 6/2003

1/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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与GS8160V32AT-300I相关器件

型号	品牌	获取价格	描述	数据表
GS8160V32AT-300IT	GSI	获取价格	Cache SRAM, 512KX32, 5ns, CMOS, PQFP100, TQFP-100
GS8160V32AT-333	GSI	获取价格	1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160V32AT-333I	GSI	获取价格	1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160V32AT-333T	GSI	获取价格	暂无描述
GS8160V32AT-350	GSI	获取价格	1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160V32AT-350I	GSI	获取价格	1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160V32BT-200	GSI	获取价格	Cache SRAM, 512KX32, 6.5ns, CMOS, PQFP100, TQFP-100
GS8160V32BT-200T	GSI	获取价格	Cache SRAM, 512KX32, 6.5ns, CMOS, PQFP100, TQFP-100
GS8160V36AGT-150	GSI	获取价格	Cache SRAM, 512KX36, 7.5ns, CMOS, PQFP100, TQFP-100
GS8160V36AGT-150I	GSI	获取价格	Cache SRAM, 512KX36, 7.5ns, CMOS, PQFP100, TQFP-100

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