5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> GS815036AGB-250T
GS815036AGB-250T PDF预览

GS815036AGB-250T

更新时间： 2024-11-12 13:07:59
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
25页 1050K
描述
Late-Write SRAM, 512KX36, 2ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119

阅读下载

中文翻译

获取价格

GS815036AGB-250T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.33
最长访问时间：2 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：18874368 bit
内存集成电路类型：LATE-WRITE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.99 mm最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS815036AGB-250T 数据手册

 浏览型号GS815036AGB-250T的Datasheet PDF文件第2页浏览型号GS815036AGB-250T的Datasheet PDF文件第3页浏览型号GS815036AGB-250T的Datasheet PDF文件第4页浏览型号GS815036AGB-250T的Datasheet PDF文件第5页浏览型号GS815036AGB-250T的Datasheet PDF文件第6页浏览型号GS815036AGB-250T的Datasheet PDF文件第7页 
Product Preview  
GS815018/36AB-357/333/300/250  
250 MHz–357 MHz  
119-Bump BGA  
Commercial Temp  
Industrial Temp  
1M x 18, 512K x 36  
18Mb Register-Register Late Write SRAM  
2.5 V V  
DD  
HSTL I/O  
Features  
Functional Description  
• Register-Register Late Write mode, Pipelined Read mode  
• 2.5 V +200/–200 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• ZQ controlled programmable output drivers  
• Dual Cycle Deselect  
Because GS815018/36A are synchronous devices, address data  
inputs and read/write control inputs are captured on the rising  
edge of the input clock. Write cycles are internally self-timed  
and initiated by the rising edge of the clock input. This feature  
eliminates complex off-chip write pulse generation required by  
asynchronous SRAMs and simplifies input signal timing.  
• Fully coherent read and write pipelines  
• Byte write operation (9-bit bytes)  
• Differential HSTL clock inputs, K and K  
• Asynchronous output enable  
• Sleep mode via ZZ  
GS815018/36A support pipelined reads utilizing a rising-edge-  
triggered output register. They also utilize a Dual Cycle  
Deselect (DCD) output deselect protocol.  
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan  
• JEDEC-standard 119-bump BGA package  
• Pb-Free 119-bump BGA package available  
GS815018/36A are implemented with high performance  
technology and are packaged in a 119-bump BGA.  
Family Overview  
Mode Control  
GS815018/36A are 18,874,368-bit (18Mb) high performance  
SRAMs. This family of wide, low voltage HSTL I/O SRAMs  
is designed to operate at the speeds needed to implement  
economical high performance cache systems.  
There are two mode control select pins (M1 and M2), which  
allow the user to set the correct read protocol for the design.  
The GS815018/36A support single clock Pipeline mode, which  
directly affects the two mode control select pins. In order for  
the part to fuction correctly, and as specified, M1 must be tied  
to VSS and M2 must be tied to V or V  
. This must be set  
DD  
DDQ  
at power-up and should not be changed during operation.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion (High)  
of the ZZ signal, or by stopping the clock (CK). Memory data is  
retained during Sleep mode.  
Parameter Synopsis  
-357  
-333  
-300  
-250  
Unit  
Pipeline  
Cycle  
tKHQV  
2.8  
1.4  
3.0  
1.5  
3.3  
1.6  
4.0  
2.0  
ns  
ns  
Curr (x18)  
Curr (x36)  
600  
650  
550  
600  
500  
550  
450  
500  
mA  
mA  
Rev: 1.05 10/2005  
1/25  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...25

中文翻译

下载PDF

与GS815036AGB-250T相关器件

型号 品牌 获取价格 描述 数据表
GS815036AGB-300 GSI

获取价格

 		1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS815036AGB-300I GSI

获取价格

 		1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS815036AGB-333 GSI

获取价格

 		1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS815036AGB-333I GSI

获取价格

 		1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS815036AGB-333IT GSI

获取价格

 		Late-Write SRAM, 512KX36, 1.5ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119
GS815036AGB-333T GSI

获取价格

 		Late-Write SRAM, 512KX36, 1.5ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119
GS815036AGB-357 GSI

获取价格

 		1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS815036AGB-357I GSI

获取价格

 		1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS815036AGB-357IT GSI

获取价格

 		Late-Write SRAM, 512KX36, 1.4ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119
GS8150F18T-11IT GSI

获取价格

 		Standard SRAM, 1MX18, 11ns, CMOS, PQFP100

与GS815036AGB-250T相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证