Datasheet > GS81332QT19CE-250MV

GS81332QT19CE-250MV

更新时间： 2024-11-13 14:57:07

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
44页	1874K
描述
165 CCGA

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GS82612QT19/37CE/LE-350M/250M(S/Q/V)

GS81332QT19/37CE/LE-350M/250M(S/Q/V)

GS8692QT19/37CE/LE-350M/250M(S/Q/V)

350 MHz–250 MHz

Rad-Hard SRAM

288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II+

165-Bump CCGA & LGA

Military Temp

1.8 V V

1.8 V and 1.5 V I/O

Features

SigmaQuad™ Family Overview

• Aerospace-Level Product

The GS82612QT19/37, GS81332QT19/37, and

• 2.0 clock Latency with DLL on

GS8692QT19/37 are built in compliance with the

• 1.0 clock Latency with DLL off

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 301,989,888-bit (288Mb),

150,994,944-bit (144Mb), and 75,497,472-bit (72Mb) SRAMs.

These SigmaQuad SRAMs are members of a family of low

power, low voltage HSTL I/O Radiation-Hardened (Rad-Hard)

SRAMs designed to operate in High Radiation environments.

• Optional DLL-controlled output timing

• Can be operated with DLL on or off

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Clocking and Addressing Schemes

The Rad-Hard SigmaQuad-II+ SRAMs are synchronous

devices. They employ two input register clock inputs, K and K.

K and K are independent single-ended clock inputs, not

differential inputs to a single differential clock input buffer.

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump Ceramic Column Grid Array (CCGA) and 165-

bump Land Grid Array (LGA) packages

Each internal read and write operation in a SigmaQuad-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaQuad-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 8M x 36 has an 4M

addressable index).

Radiation Performance

• Total Ionizing Dose (TID) > 100krads(Si)

• Single Event Latchup Immunity > 77.3 MeV.cm²/mg (125C)

Parameter Synopsis

-350M

-250M

4.0 ns

tKHKH

tKHQV

2.86 ns

0.45 ns

Rev: 1.04a 9/2021

1/44

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...44

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与GS81332QT19CE-250MV相关器件

型号	品牌	获取价格	描述	数据表
GS81332QT19CE-350M	GSI	获取价格	Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-IITM
GS81332QT19CE-350MQ	GSI	获取价格	165 CCGA
GS81332QT19CE-350MS	GSI	获取价格	165 CCGA
GS81332QT19CE-350MV	GSI	获取价格	165 CCGA
GS81332QT19LE-250MQ	GSI	获取价格	165 CLGA
GS81332QT19LE-250MS	GSI	获取价格	165 CLGA
GS81332QT19LE-250MV	GSI	获取价格	165 CLGA
GS81332QT19LE-350MQ	GSI	获取价格	165 CLGA
GS81332QT19LE-350MS	GSI	获取价格	165 CLGA
GS81332QT19LE-350MV	GSI	获取价格	165 CLGA

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