GS81314LD19/37GK-800M
800 MHz
260-Pin BGA
Military Temp
HSTL I/O
144Mb SigmaQuad-IVe™
Burst of 4 Single-Bank ECCRAM™
1.3V V
DD
1.2V ~ 1.3V V
DDQ
Features
Clocking and Addressing Schemes
• Military Temperature Range
The GS81314LD19/37GK-800M SigmaQuad-IVe ECCRAMs
are synchronous devices. They employ three pairs of positive
and negative input clocks; one pair of master clocks, CK and
CK, and two pairs of write data clocks, KD[1:0] and KD[1:0].
All six input clocks are single-ended; that is, each is received
by a dedicated input buffer.
• 4Mb x 36 and 8Mb x 18 organizations available
• Organized as a single logical memory bank
• 800 MHz operating frequency
• 933 MT/s peak transaction rate (in millions per second)
• 115 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• No address/bank restrictions on Read and Write ops
• Burst of 4 Read and Write operations
• 5 cycle Read Latency
• On-chip ECC with virtually zero SER
• Loopback signal timing training capability
• 1.3 V nominal core voltage
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IVe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g., the 8M x 18 has
2M addressable index).
• 1.2 V ~ 1.3 V HSTL I/O interface
• Configuration registers
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
SigmaQuad-IVe™ Family Overview
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
anticipated to be <0.002 FITs/Mb—a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Parameter Synopsis
V
Speed Grade
Max Operating Frequency
Read Latency
DD
-800
800 MHz
5 cycles
1.25 V to 1.35 V
Rev: 1.01 9/2020
1/39
© 2017, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.