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Datasheet > GS81285Z18T-200
GS81285Z18T-200 PDF预览

GS81285Z18T-200

更新时间： 2024-11-27 15:43:43
品牌 Logo 应用领域
GSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
24页 820K
描述
ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100

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GS81285Z18T-200 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：7.5 ns
其他特性：PIPELINED AND FLOW THROUGH ARCHITECTURE ALSO OPERATES AT 3.3V MINIMUM SUPPLY最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：150994944 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：100
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.2 A
最小待机电流：2.3 V子类别：SRAMs
最大压摆率：0.4 mA最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS81285Z18T-200 数据手册

 浏览型号GS81285Z18T-200的Datasheet PDF文件第2页浏览型号GS81285Z18T-200的Datasheet PDF文件第3页浏览型号GS81285Z18T-200的Datasheet PDF文件第4页浏览型号GS81285Z18T-200的Datasheet PDF文件第5页浏览型号GS81285Z18T-200的Datasheet PDF文件第6页浏览型号GS81285Z18T-200的Datasheet PDF文件第7页 
Preliminary  
GS81285Z18/36T-300/250/200/167  
300 MHz–167 MHz  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
144Mb 2-Die Module  
Synchronous NBT SRAM  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
Features  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization; Fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• LBO pin for Linear or Interleave Burst mode  
• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP package available  
The GS81285Z18/36T may be configured by the user to  
operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, meaning that in addition to the  
rising edge triggered registers that capture input signals, the  
device incorporates a rising-edge-triggered output register. For  
read cycles, pipelined SRAM output data is temporarily stored  
by the edge triggered output register during the access cycle  
and then released to the output drivers at the next rising edge of  
clock.  
Functional Description  
The GS81285Z18/36T is a 144Mbit Synchronous Static  
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or  
other pipelined read/double late write or flow through read/  
single late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS81285Z18/36T is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 100-pin TQFP package.  
Parameter Synopsis  
-300  
-250  
-200  
-167  
Unit  
t
2.3  
3.3  
2.5  
4.0  
3.0  
5.0  
3.4  
6.0  
ns  
ns  
KQ  
Pipeline  
3-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
550  
630  
480  
550  
420  
480  
385  
430  
mA  
mA  
t
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
8.0  
8.0  
ns  
ns  
KQ  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x32/x36)  
420  
465  
370  
405  
340  
370  
330  
360  
mA  
mA  
Packages listed with the additional “G” designator are 6/6 RoHS compliant.  
Rev: 1.00 1/2008  
1/24  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...24

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与GS81285Z18T-200相关器件

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GS81285Z18T-200I GSI

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 		ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-200IT GSI

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 		ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-200IV GSI

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 		ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-200T GSI

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 		ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-200V GSI

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 		ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-250 GSI

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 		ZBT SRAM, 8MX18, 6.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-250IT GSI

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 		ZBT SRAM, 8MX18, 6.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-250IVT GSI

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 		ZBT SRAM, 8MX18, 6.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-250VT GSI

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 		ZBT SRAM, 8MX18, 6.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-300 GSI

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 		ZBT SRAM, 8MX18, 5.5ns, CMOS, PQFP100, TQFP-100

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