Datasheet > GS81285Z18GT-250V

GS81285Z18GT-250V

更新时间： 2024-11-28 08:11:15

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
22页	781K
描述
ZBT SRAM, 8MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

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Preliminary

GS81285Z18/36T-xxxV

250 MHz–167 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

144Mb 2-Die Module

Synchronous NBT SRAM

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

Features

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

The GS81285Z18/36T-xxxV may be configured by the user

to operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

Functional Description

The GS81285Z18/36T-xxxV is a 144Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS81285Z18/36T-xxxV is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

Parameter Synopsis

-250

3.0

4.0

-200

-167

Unit

3.0

5.0

3.4

6.0

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

480

550

420

480

385

430

6.5

7.5

8.0

Flow Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

370

405

340

370

330

360

Packages listed with the additional “G” designator are 6/6 RoHS compliant.

Rev: 1.00 1/2008

1/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...22

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与GS81285Z18GT-250V相关器件

型号	品牌	获取价格	描述	数据表
GS81285Z18GT-250VT	GSI	获取价格	ZBT SRAM, 8MX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS81285Z18GT-300	GSI	获取价格	ZBT SRAM, 8MX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS81285Z18GT-300I	GSI	获取价格	ZBT SRAM, 8MX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS81285Z18GT-300IT	GSI	获取价格	ZBT SRAM, 8MX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS81285Z18GT-300T	GSI	获取价格	ZBT SRAM, 8MX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS81285Z18T-167I	GSI	获取价格	ZBT SRAM, 8MX18, 8ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-167IT	GSI	获取价格	ZBT SRAM, 8MX18, 8ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-167IVT	GSI	获取价格	ZBT SRAM, 8MX18, 8ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-200	GSI	获取价格	ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS81285Z18T-200I	GSI	获取价格	ZBT SRAM, 8MX18, 7.5ns, CMOS, PQFP100, TQFP-100

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