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GS81284Z36GB-250I PDF预览

GS81284Z36GB-250I

更新时间: 2024-11-28 14:57:11
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描述
119 BGA

GS81284Z36GB-250I 数据手册

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GS81284Z18/36B-250/200/167  
119-Bump BGA  
Commercial Temp  
Industrial Temp  
250 MHz167 MHz  
144Mb Pipelined and Flow Through  
Synchronous NBT SRAM  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Features  
Because it is a synchronous device, address, data inputs, and  
read/write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• NBT (No Bus Turn Around) functionality allows zero wait  
Read-Write-Read bus utilization; fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• ZQ mode pin for user-selectable high/low output drive  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• LBO pin for Linear or Interleave Burst mode  
• Pin-compatible with 8Mb, 16Mb, 36Mb and 72Mb devices  
• Byte write operation (9-bit Bytes)  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 119-bump BGA package  
• RoHS-compliant 119-bump BGA packages available  
The GS81284Z18/36 may be configured by the user to operate  
in Pipeline or Flow Through mode. Operating as a pipelined  
synchronous device, in addition to the rising-edge-triggered  
registers that capture input signals, the device incorporates a  
rising edge triggered output register. For read cycles, pipelined  
SRAM output data is temporarily stored by the edge-triggered  
output register during the access cycle and then released to the  
output drivers at the next rising edge of clock.  
Functional Description  
The GS81284Z18/36 is a 144Mbit Synchronous Static SRAM.  
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other  
pipelined read/double late write or flow through read/single  
late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
The GS81284Z18/36 is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
standard 119-bump BGA package.  
Parameter Synopsis  
-250  
-200  
-167  
Unit  
tKQ(x18/x36)  
tCycle  
2.5  
4.0  
3.0  
5.0  
3.4  
6.0  
ns  
ns  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x36)  
480  
550  
420  
480  
385  
430  
mA  
mA  
tKQ  
6.5  
6.5  
7.5  
7.5  
8.0  
8.0  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x36)  
370  
405  
340  
370  
330  
360  
mA  
mA  
Rev: 1.02 7/2010  
1/29  
© 2007, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

GS81284Z36GB-250I 替代型号

型号 品牌 替代类型 描述 数据表
GS81284Z36GB-200I GSI

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119 BGA
GS8128436B-167V GSI

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119 BGA
GS8128436GB-167 GSI

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