GS81280E18/32/36GT-400/333/250/200
400 MHz–200 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
8M x 18, 4M x 32, 4M x 36
144Mb Sync Burst SRAMs
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS81280E18/32/36GT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Functional Description
Applications
The GS81280E18/32/36GT is a 150,994,944-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Controls
Addresses, data I/Os, chip enables (E1 and E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS81280E18/32/36GT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
) pins are used to decouple output noise
DDQ
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-400
-333
-250
-200
Unit
tKQ
tCycle
2.5
2.5
2.5
3.0
2.5
4.0
3.0
5.0
ns
ns
Pipeline
3-1-1-1
Curr (x18)
Curr (x32/x36)
610
690
530
600
430
470
360
400
mA
mA
tKQ
tCycle
4.0
4.0
4.5
4.5
5.5
5.5
6.5
6.5
ns
ns
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
430
470
400
435
360
380
295
330
mA
mA
Rev: 1.01a 8/2017
1/22
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5秒后页面跳转
AO3401场效应管参数、引脚图、应用原理图
BT131可控硅参数及引脚图、工作原理详解
74LS32芯片参数、引脚图及功能真值表
全球首块英伟达H200交付 黄仁勋“送货上门”
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
