Datasheet > GS71108ASJ-8T

GS71108ASJ-8T

更新时间： 2024-11-06 23:54:07

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
15页	243K
描述
x8 SRAM

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中文翻译

获取价格

数据手册

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GS71108ASJ-8T 数据手册

GS71108ATP/J/SJ/U

6, 8, 10, 12 ns

SOJ, TSOP, FP-BGA

Commercial Temp

Industrial Temp

128K x 8

1Mb Asynchronous SRAM

3.3 V V

Center V and V

SOJ & TSOP-II 128K x 8-Pin Configuration

Features

• Fast access time: 6, 8, 10, 12 ns

• CMOS low power operation: 165/125/100/85 mA at

minimum cycle time

• Single 3.3 V ± 0.3 V power supply

• All inputs and outputs are TTL-compatible

• Fully static operation

DQ1

DQ2

DQ8

DQ7

32-pin

400 mil SOJ

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 32-pin SOJ package

TP: 400 mil, 32-pin TSOP Type II package

SJ: 300 mil, 32-pin SOJ package

300 mil SOJ

DQ3

DQ4

A16

A15

A14

A13

DQ6

DQ5

U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

400 mil TSOP II

Description

A10

A11

A12

The GS71108A is a high speed CMOS Static RAM organized

as 131,072 words by 8 bits. Static design eliminates the need

for external clocks or timing strobes. The GS operates on a

single 3.3 V power supply and all inputs and outputs are TTL-

compatible. The GS71108A is available in a 6 mm x 8 mm

Fine Pitch BGA package, as well as in 300 mil and 400 mil

SOJ and 400 mil TSOP Type-II packages.

Packages J, TP, and SJ

Fine Pitch BGA 128K x 8-Bump Configuration

DQ8

Pin Descriptions

DQ1 NC

DQ2 NC

Symbol

A0–A16

DQ1–DQ8

Description

Address input

NC DQ7

Data input/output

Chip enable input

Write enable input

Output enable input

+3.3 V power supply

V_SS

V_DD

V_SS

A14

A15

A16

DQ3 NC

DQ4 NC

A11 DQ5 DQ6

V_DD

A12

A13

V_SS

Ground

A10

No connect

Package U

6 mm x 8 mm, 0.75 mm Bump Pitch

Top View

Rev: 1.02 10/2001

1/15

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...15

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