GS71024T/U
8, 9, 10, 12, 15 ns
TQFP, FP-BGA
Commercial Temp
Industrial Temp
64K x 24
1.5Mb Asynchronous SRAM
3.3 V V
DD
Center V and V
DD
SS
Features
Fine Pitch BGA Bump Configuration
• Fast access time: 8, 9, 10, 12, 15 ns
• CMOS low power operation: 190/170/160/130/110 mA at
minimum cycle time.
1
2
3
4
5
6
A
B
C
D
DQ
A3
A2
A1
A0
DQ
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
DQ DQ CE2 WE DQ DQ
DQ DQ CE1 OE DQ DQ
• Industrial Temperature Option: –40 to 85°C
• Package
V
V
DQ
DQ
A5
A7
A9
A4
A6
A8
DQ
DQ
SS
DD
DD
SS
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
GT: Pb-Free 100-pin TQFP available
V
V
E
F
DQ DQ
DQ DQ
Description
G
H
DQ DQ A11 A10 DQ DQ
DQ A15 A14 A13 A12 DQ
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Pin Descriptions
Symbol
A0 to A15
X/Y
Description
Address input
Symbol
DQ1 to DQ24
Description
Data input/output
Address Multiplexer Control
Output enable input
—
Vector Input
V/S
OE
—
WE
Write enable input
Chip enable input
+3.3 V power supply
CE1, CE2
V
V
Ground
DD
SS
Block Diagram
A0
Row
Decoder
Memory Array
1024 x 1536
Address
Input
A14
Column
Decoder
A15
X/Y
0
1
Q
V/S
CE1
CE2
I/O Buffer
Control
WE
OE
DQ1
DQ24
Rev: 1.05 11/2004
1/13
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.