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GRM31CR71H105KA12L

更新时间： 2024-09-25 11:44:51
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飞思卡尔 - FREESCALE 放大器功率放大器
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17页 718K
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RF LDMOS Wideband Integrated Power Amplifiers

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Document Number: MD7IC2251N  
Rev. 0, 5/2012  
Freescale Semiconductor  
Technical Data  
RF LDMOS Wideband Integrated  
Power Amplifiers  
MD7IC2251NR1  
MD7IC2251GNR1  
The MD7IC2251N wideband integrated circuit is designed with on--chip  
matching that makes it usable from 2110--2170 MHz. This multi--stage  
structure is rated for 26 to 32 volt operation and covers all typical cellular  
base station modulation formats.  
•
Typical Doherty Single--Carrier W--CDMA Characterization Performance:  
DD = 28 Volts, IDQ1(A+B) = 80 mA, IDQ2A = 260 mA, VGS2B = 1.4 Vdc,  
V
2110--2170 MHz, 12 W AVG., 28 V  
SINGLE W--CDMA  
Pout = 12 Watts Avg., IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz,  
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.  
RF LDMOS WIDEBAND  
INTEGRATED POWER AMPLIFIERS  
G
PAE  
(%)  
Output PAR  
(dB)  
ACPR  
(dBc)  
ps  
Frequency  
2110 MHz  
2140 MHz  
2170 MHz  
(dB)  
28.8  
29.0  
29.2  
38.2  
37.9  
37.4  
7.1  
7.1  
6.9  
--34.6  
--36.2  
--36.1  
TO--270 WB--14  
PLASTIC  
MD7IC2251NR1  
•
•
Capable of Handling 10:1 VSWR, @ 32 Vdc, 2140 MHz, 63 Watts CW  
Output Power (3 dB Input Overdrive from Rated Pout  
Typical Pout @ 3 dB Compression Point ≃ 58 Watts (1)  
)
TO--270 WB--14 GULL  
PLASTIC  
MD7IC2251GNR1  
Features  
•
•
•
•
•
•
•
•
100% PAR Tested for Guaranteed Output Power Capability  
Production Tested in a Symmetrical Doherty Configuration  
Characterized with Large--Signal Load--Pull Parameters and Common Source S--Parameters  
On--Chip Matching (50 Ohm Input, DC Blocked)  
Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (2)  
Integrated ESD Protection  
225°C Capable Plastic Package  
In Tape and Reel. R1 Suffix = 500 Units, 44 mm Tape Width, 13 inch Reel.  
V
DS1A  
Carrier  
(3)  
CARRIER  
RF /V  
V
1
2
DS1A  
GS2A  
V
V
RF  
inA  
out1 DS2A  
14  
13  
3
GS1A  
RF  
RF /V  
out1 DS2A  
4
inA  
NC  
NC  
NC  
NC  
5
6
V
V
GS1A  
GS2A  
Quiescent Current  
Temperature Compensation  
7
(2)  
(2)  
8
RF  
9
RF /V  
out2 DS2B  
inB  
V
V
GS1B  
GS2B  
Quiescent Current  
Temperature Compensation  
V
10  
11  
GS1B  
GS2B  
V
V
12 Peaking  
DS1B  
(3)  
PEAKING  
RF /V  
(Top View)  
RF  
inB  
out2 DS2B  
Note: Exposed backside of the package is  
the source terminal for the transistors.  
V
DS1B  
Figure 1. Functional Block Diagram  
Figure 2. Pin Connections  
1. P3dB =P +7.0 dB whereP  
is the averageoutput power measured using an unclipped W--CDMA single--carrier input signal where output  
avg  
avg  
PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.  
2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control  
for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf. Select Documentation/ApplicationNotes -- AN1977 orAN1987.  
3. Peaking and Carrier orientation is determined by the test fixture design.  
© Freescale Semiconductor, Inc., 2012. All rights reserved.  
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