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GP2015/1G/FP2Q PDF预览

GP2015/1G/FP2Q

更新时间: 2024-01-17 19:45:26
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信电信集成电路
页数 文件大小 规格书
24页 212K
描述
Telecom Circuit, 1-Func, CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BBC, LQFP-48

GP2015/1G/FP2Q 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:LFQFP, QFP48,.35SQ,20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm湿度敏感等级:3
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Other Telecom ICs
最大压摆率:0.077 mA标称供电电压:3 V
表面贴装:YES技术:CMOS
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm

GP2015/1G/FP2Q 数据手册

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GP2015  
GPS Receiver RF Front End  
Sept. 2007  
The GP2015 is a small format RF Front-end for Global  
Positioning System (GPS) receivers. Equivalent in  
performance to the GP2010 but in a TQFP package, this  
product is suited for size-critical applications as the RF area  
can be reduced by a factor of two to three using miniature  
surfacemountpassivecomponents TheGP2015isdesigned  
to operate from either 3 or 5 Volt supplies.  
Ordering Information  
GP2015/1G/FP1N  
GP2015/IG/FP1Q  
48 Pin LQFP  
48 Pin LQFP  
Trays, Bake & Drypack  
Tape & Reel, Bake & Drypack  
Tape & Reel, Bake & Drypack  
Trays, Bake & Drypack  
GP2015/1G/FP2Q 48 Pin LQFP*  
GP2015/1G/FP2N  
48 Pin LQFP*  
*Pb Free Matte Tin  
The input to the device is the L1 (1575.42MHz) Coarse-  
Acquisition (C/A) code Global Positioning signal from an  
antenna (via a low-noise pre-amplifier). The output is 2-bit  
quantised for subsequent signal processing in the digital  
domain.TheGP2015containsanon-chipsynthesiser,mixers,  
AGC and a quantiser which provides Sign and Magnitude  
digitaloutputs.Aminimumofexternalcomponentsisrequired  
to make a complete GPS front-end.  
36 35 34 33 32 31 30 29 28 27 26 25  
37  
38  
39  
24  
23  
22  
40  
41  
21  
20  
42  
19  
GP2015  
ThedevicehasbeendesignedtooperatewiththeGP2021  
12-channel GPS Correlator and GP4020 GPS Baseband  
Processor, both available from Zarlink Semiconductor.  
43  
44  
18  
17  
45  
46  
47  
48  
16  
15  
14  
13  
Features  
 Ultra miniature TQFP package  
 Low Voltage Operation (3V - 5V)  
 Low Power - 200mW typ. (3V supply)  
 C/A Code Compatible  
 On-chip PLL Including Complete VCO  
 Triple Conversion Receiver  
 48-Lead Surface Mount Quad Flat-Pack Package  
 Sign and Magnitude Digital Outputs  
 Compatible with GP2021 and GP4020 Correlators  
1
2
3
4
5
6
7
8
9
10 11 12  
FP48  
Pin  
Name  
Pin  
25 N/C  
26 CC (DIG)  
27 REF 2  
28 REF 1  
29  
30  
31  
Name  
1
2
3
4
5
6
7
8
9
IF Output  
PLL Filter 1  
PLL Filter 2  
V
V
V
V
V
EE (OSC)  
CC (OSC)  
EE (OSC)  
EE (REG)  
V
V
V
CC (RF)  
EE (RF)  
EE (RF)  
PRef  
PReset  
VEE (IO)  
32 RF Input  
33  
34  
35  
VEE (RF)  
VEE (RF)  
VCC (RF)  
10  
11 CLK  
Applications  
 C/A Code Global Positioning by Satellite Receivers  
 Time Standards  
 Navigation  
12 N/C  
13 N/C  
14 MAG  
15 SIGN  
16 OPCIK-  
17 OPCIK+  
36 N/C  
37 O/P 1-  
38 O/P 1+  
39  
VCC (2)  
40 I/P 2-  
41 I/P 2+  
• Surveying  
18  
V
DD (IO)  
42  
43  
V
V
EE (IF)  
EE (IF)  
Related Products and Publications  
19 PDN  
20 TEST  
21 LD  
Data  
Reference  
Part  
Description  
44 O/P 2-  
45 O/P 2+  
22  
23 AGC -  
24  
V
EE (DIG)  
46  
VCC (3)  
GP2021  
GP4020  
Twelve-Channel Correlator  
GPS Baseband Processor  
DS4057  
47 I/P 3-  
48 I/P 3+  
DS5134  
AN4808  
AGC +  
App. Note  
GPS ORION 12 Channel GPS  
Receiver Reference Design  
Figure 1 - Pin connections - top view  
App Note.  
App. Brief  
GP2000 GPS Receiver  
Hardware Design  
AN4855  
AB5202  
GP2010/GP2015: Using Murata  
SAFJA35M4WC0Z00 SAW Filter  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2002-2007, Zarlink Semiconductor Inc. All Rights Reserved.  

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