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GAL22V10B-25LJI PDF预览

GAL22V10B-25LJI

更新时间： 2024-11-09 22:35:39
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
29页 387K
描述
High Performance E2CMOS PLD Generic Array Logic

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中文翻译

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GAL22V10B-25LJI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-28
针数：28Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.75Is Samacsys：N
其他特性：REGISTER PRELOAD; POWER-UP RESET架构：PAL-TYPE
最大时钟频率：33.3 MHzJESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.5062 mm
湿度敏感等级：1专用输入次数：11
I/O 线路数量：10输入次数：22
输出次数：10产品条款数：132
端子数量：28最高工作温度：85 °C
最低工作温度：-40 °C组织：11 DEDICATED INPUTS, 10 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：5 V可编程逻辑类型：EE PLD
传播延迟：25 ns认证状态：Not Qualified
座面最大高度：4.572 mm子类别：Programmable Logic Devices
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：11.5062 mmBase Number Matches：1

GAL22V10B-25LJI 数据手册

 浏览型号GAL22V10B-25LJI的Datasheet PDF文件第2页浏览型号GAL22V10B-25LJI的Datasheet PDF文件第3页浏览型号GAL22V10B-25LJI的Datasheet PDF文件第4页浏览型号GAL22V10B-25LJI的Datasheet PDF文件第5页浏览型号GAL22V10B-25LJI的Datasheet PDF文件第6页浏览型号GAL22V10B-25LJI的Datasheet PDF文件第7页 
GAL22V10  
High Performance E2CMOS PLD  
Generic Array Logic™  
Functional Block Diagram  
Features  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 4 ns Maximum Propagation Delay  
— Fmax = 250 MHz  
RESET  
I/CLK  
8
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I/O/Q  
I/O/Q  
— 3.5 ns Maximum from Clock Input to Data Output  
I
I
I
I
I
I
— UltraMOS® Advanced CMOS Technology  
10  
12  
• ACTIVE PULL-UPS ON ALL PINS  
• COMPATIBLE WITH STANDARD 22V10 DEVICES  
— Fully Function/Fuse-Map/Parametric Compatible  
with Bipolar and UVCMOS 22V10 Devices  
I/O/Q  
I/O/Q  
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR  
— 90mA Typical Icc on Low Power Device  
— 45mA Typical Icc on Quarter Power Device  
14  
16  
16  
14  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
I/O/Q  
I/O/Q  
I
I
• TEN OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
12  
10  
• PRELOAD AND POWER-ON RESET OF REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I
I
8
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
ESCRIPTION  
PRESET  
Pin Configuration  
Description  
DIP  
The GAL22V10, at 4ns maximum propagation delay time, combines  
a high performance CMOS process with Electrically Erasable (E2)  
floating gate technology to provide the highest performance avail-  
able of any 22V10 device on the market. CMOS circuitry allows  
the GAL22V10 to consume much less power when compared to  
bipolar 22V10 devices. E2 technology offers high speed (<100ms)  
erase times, providing the ability to reprogram or reconfigure the  
device quickly and efficiently.  
PLCC  
1
6
Vcc  
24  
I/CLK  
I/O/Q  
I
I
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
4
2
28  
26  
5
7
25  
23  
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
GAL  
22V10  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. The GAL22V10 is fully function/fuse map/parametric com-  
patible with standard bipolar and CMOS 22V10 devices.  
GAL22V10  
Top View  
NC  
NC  
18  
I
I
I
I
I
9
21  
19  
I/O/Q  
I/O/Q  
I/O/Q  
11  
I
12  
14  
16  
18  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lat-  
tice Semiconductor delivers 100% field programmability and func-  
tionality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
I
I
GND  
12  
13  
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2000  
22v10_06  
1
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