5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> GAL20V8B-25QPNI
GAL20V8B-25QPNI PDF预览

GAL20V8B-25QPNI

更新时间： 2024-11-08 03:39:43
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
25页 578K
描述
High Performance E2CMOS PLD Generic Array Logic⑩

阅读下载

中文翻译

获取价格

GAL20V8B-25QPNI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：DIP
包装说明：LEAD FREE, PLASTIC, DIP-24针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.64
Is Samacsys：N架构：PAL-TYPE
最大时钟频率：37 MHzJESD-30 代码：R-PDIP-T24
JESD-609代码：e3长度：31.75 mm
专用输入次数：12I/O 线路数量：8
输入次数：20输出次数：8
产品条款数：64端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
组织：12 DEDICATED INPUTS, 8 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V可编程逻辑类型：EE PLD
传播延迟：25 ns认证状态：Not Qualified
座面最大高度：5.334 mm子类别：Programmable Logic Devices
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

GAL20V8B-25QPNI 数据手册

 浏览型号GAL20V8B-25QPNI的Datasheet PDF文件第2页浏览型号GAL20V8B-25QPNI的Datasheet PDF文件第3页浏览型号GAL20V8B-25QPNI的Datasheet PDF文件第4页浏览型号GAL20V8B-25QPNI的Datasheet PDF文件第5页浏览型号GAL20V8B-25QPNI的Datasheet PDF文件第6页浏览型号GAL20V8B-25QPNI的Datasheet PDF文件第7页 
GAL20V8  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 5 ns Maximum Propagation Delay  
— Fmax = 166 MHz  
I/CLK  
I
IMUX  
I
CLK  
— 4 ns Maximum from Clock Input to Data Output  
— UltraMOS® Advanced CMOS Technology  
I/O/Q  
8
8
OLMC  
I
I
I
I
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR  
— 75mA Typ Icc on Low Power Device  
— 45mA Typ Icc on Quarter Power Device  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
8
8
8
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
I
I
— Also Emulates 24-pin PAL® Devices with Full Function/  
Fuse Map/Parametric Compatibility  
8
8
8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
I
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
OLMC  
IMUX  
I
I
OE  
I
I/OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
• LEAD-FREE PACKAGE OPTIONS  
Description  
Pin Configuration  
The GAL20V8C, at 5ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide the highest speed  
performance available in the PLD market. High speed erase times  
(<100ms) allow the devices to be reprogrammed quickly and ef-  
ficiently.  
DIP  
PLCC  
1
Vcc  
24  
I/CLK  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
I
I
I
I
GAL  
4
2
28  
26  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configura-  
tions possible with the GAL20V8 are the PAL architectures listed  
in the table of the macrocell description section. GAL20V8 devices  
are capable of emulating any of these PAL architectures with full  
function/fuse map/parametric compatibility.  
20V8  
5
7
I
I
I
25 I/O/Q  
I/O/Q  
23  
6
I/O/Q  
NC  
GAL20V8  
Top View  
NC  
18  
I
I
I
I
I
9
21 I/O/Q  
I/O/Q  
I
I
I
11  
19  
18  
I/O/Q  
12  
14  
16  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
12  
13 I/OE  
GND  
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
20v8_07  
1
1234567...25

中文翻译

下载PDF

GAL20V8B-25QPNI 替代型号

型号 品牌 替代类型 描述 数据表
GAL20V8B-25QPI LATTICE

完全替代

 High Performance E2CMOS PLD Generic Array Logic
GAL20V8B-25QPN LATTICE

类似代替

 High Performance E2CMOS PLD Generic Array Log
GAL20V8B-25QP LATTICE

功能相似

 High Performance E2CMOS PLD Generic Array Logic

与GAL20V8B-25QPNI相关器件

型号 品牌 获取价格 描述 数据表
GAL20V8B-7LI LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Logic
GAL20V8B-7LJ LATTICE

获取价格

 		Electrically-Erasable PLD
GAL20V8B-7LP LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Logic
GAL20V8B-7LPN LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Log
GAL20V8C-10LJ LATTICE

获取价格

 		Electrically-Erasable PLD
GAL20V8C-10LJI LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Logic
GAL20V8C-10LJN LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Log
GAL20V8C-10LJNI LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Log
GAL20V8C-10LP LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Logic
GAL20V8C-5LJ LATTICE

获取价格

 		High Performance E2CMOS PLD Generic Array Logic

与GAL20V8B-25QPNI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证