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GAL20RA10B-15LP PDF预览

GAL20RA10B-15LP

更新时间： 2024-11-07 22:51:03
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
15页 241K
描述
High-Speed Asynchronous E2CMOS PLD Generic Array Logic⑩

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中文翻译

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GAL20RA10B-15LP 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：PLASTIC, DIP-24针数：24
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.75
Is Samacsys：N其他特性：REGISTER PRELOAD; POWER-UP RESET
架构：PAL-TYPE最大时钟频率：45 MHz
JESD-30 代码：R-PDIP-T24JESD-609代码：e0
长度：31.75 mm专用输入次数：10
I/O 线路数量：10输入次数：20
输出次数：10产品条款数：80
端子数量：24最高工作温度：75 °C
最低工作温度：组织：10 DEDICATED INPUTS, 10 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：225电源：5 V
可编程逻辑类型：EE PLD传播延迟：15 ns
认证状态：Not Qualified座面最大高度：5.334 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn85Pb15)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.62 mmBase Number Matches：1

GAL20RA10B-15LP 数据手册

 浏览型号GAL20RA10B-15LP的Datasheet PDF文件第2页浏览型号GAL20RA10B-15LP的Datasheet PDF文件第3页浏览型号GAL20RA10B-15LP的Datasheet PDF文件第4页浏览型号GAL20RA10B-15LP的Datasheet PDF文件第5页浏览型号GAL20RA10B-15LP的Datasheet PDF文件第6页浏览型号GAL20RA10B-15LP的Datasheet PDF文件第7页 
GAL20RA10  
High-Speed Asynchronous E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 7.5 ns Maximum Propagation Delay  
— Fmax = 83.3 MHz  
PL  
— 9 ns Maximum from Clock Input to Data Output  
8
OLMC  
I/O/Q  
I/O/Q  
I
I
I
I
I
I
I
I
I
I
— TTL Compatible 8 mA Outputs  
— UltraMOS® Advanced CMOS Technology  
8
8
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR  
— 75mA Typical Icc  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100 ms)  
— 20 Year Data Retention  
I/O/Q  
I/O/Q  
8
8
8
8
8
8
I/O/Q  
I/O/Q  
• TEN OUTPUT LOGIC MACROCELLS  
— Independent Programmable Clocks  
— Independent Asynchronous Reset and Preset  
— Registered or Combinatorial with Polarity  
— Full Function and Parametric Compatibility with  
PAL20RA10  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— State Machine Control  
— Standard Logic Consolidation  
— Multiple Clock Logic Designs  
8
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
Description  
OE  
The GAL20RA10 combines a high performance CMOS process  
with electrically erasable (E2) floating gate technology to provide  
the highest speed performance available in the PLD market. Lattice  
Semiconductor’s E2CMOS circuitry achieves power levels as low  
as 75mA typical ICC which represents a substantial savings in power  
when compared to bipolar counterparts. E2 technology offers high  
speed (<100ms) erase times providing the ability to reprogram,  
reconfigure or test the devices quickly and efficiently.  
Pin Configuration  
DIP  
1
Vcc  
24  
PLCC  
PL  
I/O/Q  
I
I
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
GAL  
4
2
28  
26  
5
7
I
25  
I/O/Q  
I/O/Q  
20RA10  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. The GAL20RA10 is a direct parametric compatible CMOS  
replacement for the PAL20RA10 device.  
I
I
6
23 I/O/Q  
NC  
18  
I
I
GAL20RA10  
Top View  
NC  
I
I
I
9
21  
I/O/Q  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacturing. Therefore, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
I
I
I
I/O/Q  
11  
19  
18  
I/O/Q  
12  
14  
16  
GND  
13 OE  
12  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com  
July 1997  
1
20ra10_02  
1234567...15

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