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GAL20LV8D-7LJ PDF预览

GAL20LV8D-7LJ

更新时间： 2024-09-19 22:51:03
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
17页 284K
描述
Low Voltage E2CMOS PLD Generic Array Logic

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中文翻译

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GAL20LV8D-7LJ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：PLASTIC, LCC-28
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
其他特性：REGISTER PRELOAD; POWER-UP RESET架构：PAL-TYPE
最大时钟频率：100 MHzJESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.5062 mm
湿度敏感等级：1专用输入次数：12
I/O 线路数量：8输入次数：20
输出次数：8产品条款数：64
端子数量：28最高工作温度：75 °C
最低工作温度：组织：12 DEDICATED INPUTS, 8 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：225电源：3.3 V
可编程逻辑类型：EE PLD传播延迟：7.5 ns
认证状态：Not Qualified座面最大高度：4.572 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn85Pb15)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.5062 mmBase Number Matches：1

GAL20LV8D-7LJ 数据手册

 浏览型号GAL20LV8D-7LJ的Datasheet PDF文件第2页浏览型号GAL20LV8D-7LJ的Datasheet PDF文件第3页浏览型号GAL20LV8D-7LJ的Datasheet PDF文件第4页浏览型号GAL20LV8D-7LJ的Datasheet PDF文件第5页浏览型号GAL20LV8D-7LJ的Datasheet PDF文件第6页浏览型号GAL20LV8D-7LJ的Datasheet PDF文件第7页 
GAL20LV8  
Low Voltage E2CMOS PLD  
Generic Array Logic™  
Functional Block Diagram  
Features  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 3.5 ns Maximum Propagation Delay  
— Fmax = 250 MHz  
— 2.5 ns Maximum from Clock Input to Data Output  
— UltraMOS® Advanced CMOS Technology  
— TTL-Compatible Balanced 8mA Output Drive  
I/CLK  
I
IMUX  
I
CLK  
I/O/Q  
OLMC  
8
8
I
I
I
I
• 3.3V LOW VOLTAGE 20V8 ARCHITECTURE  
— JEDEC-Compatible 3.3V Interface Standard  
— 5V Compatible Inputs  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
8
8
8
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
I
I
8
8
8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— Glue Logic for 3.3V Systems  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I
OLMC  
IMUX  
I
I
OE  
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
I/OE  
Description  
Pin Configuration  
The GAL20LV8D, at 3.5 ns maximum propagation delay time,  
provides the highest speed performance available in the PLD  
market. The GAL20LV8D is manufactured using Lattice  
Semiconductor's advanced 3.3V E2CMOS process, which com-  
bines CMOS with Electrically Erasable (E2) floating gate technology.  
High speed erase times (<100ms) allow the devices to be repro-  
grammed quickly and efficiently.  
PLCC  
4
2
28  
26  
5
7
I
I
I
25 I/O/Q  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configura-  
tions possible with the GAL20LV8D are the PAL architectures listed  
in the table of the macrocell description section. GAL20LV8D  
devices are capable of emulating any of these PAL architectures  
with full function/fuse map compatibility.  
I/O/Q  
23  
I/O/Q  
NC  
GAL20LV8D  
Top View  
NC  
I
I
I
9
21 I/O/Q  
I/O/Q  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
11  
19  
18  
I/O/Q  
12  
14  
16  
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
March 2000  
1
20lv8_05  
1234567...17

中文翻译

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GAL20LV8D-7LJ 替代型号

型号 品牌 替代类型 描述 数据表
GAL20LV8D-5LJ LATTICE

完全替代

 Low Voltage E2CMOS PLD Generic Array Logic
GAL20LV8D-3LJ LATTICE

完全替代

 Low Voltage E2CMOS PLD Generic Array Logic

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