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GAL18V10B-15LJ PDF预览

GAL18V10B-15LJ

更新时间： 2024-09-19 22:37:15
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
16页 267K
描述
High Performance E2CMOS PLD Generic Array Logic

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中文翻译

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GAL18V10B-15LJ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：PLASTIC, LCC-20针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.79
Is Samacsys：N其他特性：REGISTER PRELOAD; POWER-UP RESET
架构：PAL-TYPE最大时钟频率：55.5 MHz
JESD-30 代码：S-PQCC-J20JESD-609代码：e0
长度：8.9662 mm湿度敏感等级：1
专用输入次数：7I/O 线路数量：10
输入次数：18输出次数：10
产品条款数：96端子数量：20
最高工作温度：75 °C最低工作温度：
组织：7 DEDICATED INPUTS, 10 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC20,.4SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：5 V可编程逻辑类型：EE PLD
传播延迟：15 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子面层：Tin/Lead (Sn85Pb15)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：8.9662 mm
Base Number Matches：1

GAL18V10B-15LJ 数据手册

 浏览型号GAL18V10B-15LJ的Datasheet PDF文件第2页浏览型号GAL18V10B-15LJ的Datasheet PDF文件第3页浏览型号GAL18V10B-15LJ的Datasheet PDF文件第4页浏览型号GAL18V10B-15LJ的Datasheet PDF文件第5页浏览型号GAL18V10B-15LJ的Datasheet PDF文件第6页浏览型号GAL18V10B-15LJ的Datasheet PDF文件第7页 
GAL18V10  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 7.5 ns Maximum Propagation Delay  
— Fmax = 111 MHz  
RESET  
I/CLK  
— 5.5 ns Maximum from Clock Input to Data Output  
8
— TTL Compatible 16 mA Outputs  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I/O/Q  
I/O/Q  
— UltraMOS® Advanced CMOS Technology  
8
8
I
I
I
I
I
I
I
• LOW POWER CMOS  
— 75 mA Typical Icc  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
I/O/Q  
I/O/Q  
8
10  
10  
8
I/O/Q  
I/O/Q  
• TEN OUTPUT LOGIC MACROCELLS  
— Uses Standard 22V10 Macrocell Architecture  
— Maximum Flexibility for Complex Logic Designs  
• PRELOAD AND POWER-ON RESET OF REGISTERS  
— 100% Functional Testability  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
8
8
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
8
Description  
PRESET  
The GAL18V10, at 7.5 ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide a very flexible 20-pin  
PLD. CMOS circuitry allows the GAL18V10 to consume much less  
power when compared to its bipolar counterparts. The E2 technol-  
ogy offers high speed (<100ms) erase times, providing the ability  
to reprogram or reconfigure the device quickly and efficiently.  
Pin Configuration  
DIP  
PLCC  
1
20  
Vcc  
I/CLK  
By building on the popular 22V10 architecture, the GAL18V10  
eliminates the learning curve usually associated with using a new  
device architecture. The generic architecture provides maximum  
design flexibility by allowing the Output Logic Macrocell (OLMC)  
to be configured by the user. The GAL18V10 OLMC is fully com-  
patible with the OLMC in standard bipolar and CMOS 22V10 de-  
vices.  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
I
I
I
I
I/CLK Vcc I/O/Q  
20  
2
GAL  
18  
I/O/Q  
I/O/Q  
4
6
I
18V10  
I
I
5
I
I
GAL18V10  
Top View  
16 I/O/Q  
I/O/Q  
15  
I
I
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
I
I
I/O/Q  
14  
8
9
11  
13  
I/O/Q GND I/O/Q I/O/Q I/O/Q  
I/O/Q  
GND  
10  
11  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com  
July 1997  
1
18v10_03  
1234567...16

中文翻译

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GAL18V10B-15LJ 替代型号

型号 品牌 替代类型 描述 数据表
GAL18V10B-20LJ LATTICE

类似代替

 High Performance E2CMOS PLD Generic Array Logic
GAL18V10B-10LJ LATTICE

类似代替

 High Performance E2CMOS PLD Generic Array Logic
GAL18V10B-15LJN LATTICE

功能相似

 EE PLD, 15ns, CMOS, PQCC20, LEAD FREE, PLASTIC, LCC-20

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