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GAL16LV8C-7LJN PDF预览

GAL16LV8C-7LJN

更新时间： 2024-12-01 03:09:15
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
22页 282K
描述
Low Voltage E2CMOS PLD Generic Array Logic⑩

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中文翻译

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GAL16LV8C-7LJN 数据手册

 浏览型号GAL16LV8C-7LJN的Datasheet PDF文件第2页浏览型号GAL16LV8C-7LJN的Datasheet PDF文件第3页浏览型号GAL16LV8C-7LJN的Datasheet PDF文件第4页浏览型号GAL16LV8C-7LJN的Datasheet PDF文件第5页浏览型号GAL16LV8C-7LJN的Datasheet PDF文件第6页浏览型号GAL16LV8C-7LJN的Datasheet PDF文件第7页 
GAL16LV8  
Low Voltage E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 3.5 ns Maximum Propagation Delay  
— Fmax = 250 MHz  
I/CLK  
CLK  
— 2.5 ns Maximum from Clock Input to Data Output  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
8
8
— UltraMOS® Advanced CMOS Technology  
OLMC  
I
I
I
I
I
I
I
I
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE  
— JEDEC-Compatible 3.3V Interface Standard  
— 5V Compatible Inputs  
— I/O Interfaces with Standard 5V TTL Devices  
(GAL16LV8C)  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
8
8
8
8
8
8
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— Glue Logic for 3.3V Systems  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I/O/Q  
I/OE  
OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
• LEAD-FREE PACKAGE OPTIONS  
Description  
Pin Configuration  
The GAL16LV8D, at 3.5 ns maximum propagation delay time,  
provides the highest speed performance available in the PLD  
market. The GAL16LV8C can interface with both 3.3V and 5V  
signal levels. The GAL16LV8 is manufactured using Lattice  
Semiconductor's advanced 3.3V E2CMOS process, which com-  
bines CMOS with Electrically Erasable (E2) floating gate technology.  
High speed erase times (<100ms) allow the devices to be repro-  
grammed quickly and efficiently.  
PLCC  
I
I
I/CLK Vcc I/O/Q  
20  
2
18  
I/O/Q  
4
6
I
I/O/Q  
I/O/Q  
I
The 3.3V GAL16LV8 uses the same industry standard 16V8 archi-  
tecture as its 5V counterpart and supports all architectural features  
such as combinatorial or registered macrocell operations.  
GAL16LV8  
Top View  
16  
I
I/O/Q  
I/O/Q  
I
Unique test circuitry and reprogrammable cells allow complete AC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
14  
I
8
9
I
11  
13  
GND I/OE I/O/Q I/O/Q  
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2004  
16lv8_05  
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GAL16LV8C-7LJN 替代型号

型号 品牌 替代类型 描述 数据表
GAL16LV8C-15LJN LATTICE

完全替代

 Low Voltage E2CMOS PLD Generic Array Logic⑩
GAL16LV8C-10LJN LATTICE

完全替代

 Low Voltage E2CMOS PLD Generic Array Logic⑩
GAL16LV8C-15LJ LATTICE

完全替代

 Low Voltage E2CMOS PLD Generic Array Logic

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