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GaAs PLL Frequency Multiplier
TECHNICAL DATA
DIP PIN ASSIGNMENT
The GA Series of frequency multipliers comprises a set of
three phase-locked loop integrated circuits to generate high
frequency crystal controlled outputs. All three devices are
implemented using Gallium Arsenide Technology.
Applications include SONET and RF wireless systems
requiring low phase jitter.
GA01 - PT
GA02 - PT
GA03 - PT
To increase the usable output frequency range of the device,
three divide by two prescalars are available. All prescalar
outputs are ECL compatible. External components required
for operation are: (1) loop filter; and (2) reference input.
The external reference can be stable or variable such as a
VCXO.
SM PIN ASSIGNMENT
NQ3
Q3
Q2
NQ2
GA01 - PS
GA02 - PS
GA03 - PS
Vcc
Q1
LOGIC DIAGRAM
Vee
NQ1
REF IN
TUNE
BARE DIE PAD ASSIGNMENT
*- Back side of Die must be biased to Vcc
-------24
GA01 - DG
GA02 - DG
GA03 - DG
-------17
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Gnd
Vcc
Reset_in
Vcc
9---------
PAD
1
2
3
4
5
6
7
CONNECTION
Gnd
PVcc
Nref_out
Vref_in
Ref_in
PVcc
Vcc
Gnd
Gnd
AGnd
Iout
Tune
Gnd
Q_25
PVcc
Gnd
PVcc
Q3
NQ3
PVcc
Q2
NQ2
PVcc
Q1
ORDERING INFORMATION
An internal passive lag loop filter can be included internal
to the package suffixes PT and PS. Add an additional “F”
to the end of the suffix for internal loop filter option. Loop
filter components values are given in the design example
AN-95 GaAs PLL Application Note. For additional loop
filter options contact the factory.
8
9
10
11
12
13
14
15
AVcc
AVcc
AGnd
NQ1
PVcc
INT
Specifications subject to change without notice.
DATA SHEET #: __G_A__0_0_0_____ PAGE____1__ OF ___4____ REV:__0_5_____ DATE:____1_2_/4_/_9_8___ © Copyright 1998 Connor-Winfield all rights reserved.