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FZL4146G PDF预览

FZL4146G

更新时间: 2024-09-14 22:32:15
品牌 Logo 应用领域
英飞凌 - INFINEON 外围驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
14页 412K
描述
Quad Driver Incl. Short-Circuit Signaling

FZL4146G 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.86
Is Samacsys:N内置保护:OVER CURRENT
接口集成电路类型:BUFFER OR INVERTER BASED PERIPHERAL DRIVERJESD-30 代码:R-PDSO-G20
长度:12.8 mm功能数量:4
端子数量:20最高工作温度:125 °C
最低工作温度:-25 °C输出电流流向:SOURCE
标称输出峰值电流:0.0016 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:4.5/40 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Peripheral Drivers
最大供电电压:40 V最小供电电压:4.5 V
表面贴装:YES技术:BIPOLAR
温度等级:OTHER端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.6 mmBase Number Matches:1

FZL4146G 数据手册

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FZL 4146  
Quad Driver Incl. Short-Circuit Signaling  
Bipolar IC  
Features  
Short-circuit signaling  
Four driver circuits for driving power transistors  
Turn-ON threshold setting from 1.5 to 7 V  
P-DSO-20-7  
Package  
Type  
Ordering Code  
FZL 4146 G  
Q67000-H8743  
P-DSO-20-7 (SMD)  
General Description  
The IC comprises four driver circuits capable of driving power transistors (PNP or  
PMOS). The output transistors are protected against short-circuit to ground and supply  
voltage. The turn-ON threshold can be set from 1.5 V to 7 V. Overload at one or several  
outputs will be indicated at pin SQ (signaling output). The corresponding power  
transistors are then protected by changeover to clock-governed operation.  
Circuit Description  
Each driver circuit has one active high driver input Dl and a common enable input ENA  
(active high) is provided for all stages. The Q output is designed to drive the output  
transistors. The load current is sampled and, if necessary, limited via pin W. If the load  
current exceeds the preset value, the output stage switches off. Switching-ON again is  
provided by the built-in clock generator T. Its operation requires an external capacitor Ce  
at pin CE. If Ce is bridged by a break-key, switching-ON can only be carried out by  
operating this key. The duty cycle of the clock generator is 1:47 (e.g. 45 µs/2.1 ms with  
Ce = 10 nF). The clock generator is privileged versus the current sensor shut down.  
When the supply is connected, the internal RS-FF goes into the state corresponding to  
the released output.  
Semiconductor Group  
1
03.96  

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