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FSTUD162450MTD PDF预览

FSTUD162450MTD

更新时间: 2024-09-24 22:17:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 开关
页数 文件大小 规格书
11页 564K
描述
Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting and 25з Series Resistors in Outputs

FSTUD162450MTD 数据手册

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April 2001  
Revised August 2001  
FSTUD162450  
Configurable 4-Bit to 20-Bit Bus Switch with  
2V Undershoot Protection and Selectable Level Shifting  
and 25Series Resistors in Outputs  
General Description  
Features  
The Fairchild Universal Bus Switch FSTUD162450 pro-  
vides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed  
CMOS TTL-compatible bus switching. The low On Resis-  
tance of the switch allows inputs to be connected to out-  
puts without adding propagation delay or generating  
additional ground bounce noise.  
Undershoot protected to 2V (A and B Ports)  
Voltage level shifting  
25switch connection between two ports  
Minimal propagation delay through the switch  
Low lCC  
The FSTUD162450 is designed to allow “customer” config-  
uration control of the enable connections. The device can  
be organized as either a five 4-bit, four 5-bit, two 10-bit or  
one 20-bit bus switch. Also available are 8-bit and 16-bit  
enabled configurations (see Functional Description). The  
device's bit configuration is controlled through select pin  
logic. (see Truth Table). When OEx is LOW, Port Ax is con-  
Zero bounce in flow-through mode  
Control inputs compatible with TTL level  
See Applications Notes AN-5008 and AN-5021  
for UHC details  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA) (Preliminary)  
nected to Port Bx. When OEx is HIGH, the switch is OPEN.  
Applications Note  
Select pins S0, S1, S2 are intended to be used as static  
user configurable control pins. The AC performance of  
these pins has not been characterized or tested. Switching  
of these select pins during system operation may tempo-  
rarily disrupt output logic states and/or enable pin controls.  
The A and B Ports are protected against undershoot to  
support an extended range to 2.0V below ground.  
Fairchild's integrated Undershoot Hardened Circuit  
(UHC ) senses undershoot at the I/O and responds by  
preventing voltage differentials from developing and turn-  
ing the switch on.  
Another innovative device feature is the addition of a level  
shifting select pin, “S2”. When S2 is LOW, the device  
behaves as a standard N-MOS switch. When S2 is HIGH, a  
diode to VCC is integrated into the circuit allowing for level  
shifting between 5V inputs and 3.3V outputs.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
FSTUD162450GX  
(Note 1)  
BGA54A  
Preliminary  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[Tape and Reel]  
FSTUD162450MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Note 1: BGA package available in Tape and Reel only.  
UHC is a trademark of Fairchild Semiconductor Corporation.  
© 2001 Fairchild Semiconductor Corporation  
DS500469  
www.fairchildsemi.com  

FSTUD162450MTD 替代型号

型号 品牌 替代类型 描述 数据表
FSTUD162450MTDX FAIRCHILD

完全替代

BUS SWITCH|CMOS|TSSOP|56PIN|PLASTIC

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