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FSTUD16211MTDX PDF预览

FSTUD16211MTDX

更新时间： 2024-09-24 23:52:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 开关
页数 文件大小 规格书
8页 303K
描述
Bus Switch

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中文翻译

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FSTUD16211MTDX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：unknown
风险等级：5.26其他特性：TTL COMPATIBLE BUS SWITCH
系列：CBT/FST/QS/5C/BJESD-30 代码：R-PDSO-G56
JESD-609代码：e3长度：14 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：2
位数：12功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：5 V传播延迟（tpd）：0.25 ns
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mm

FSTUD16211MTDX 数据手册

 浏览型号FSTUD16211MTDX的Datasheet PDF文件第2页浏览型号FSTUD16211MTDX的Datasheet PDF文件第3页浏览型号FSTUD16211MTDX的Datasheet PDF文件第4页浏览型号FSTUD16211MTDX的Datasheet PDF文件第5页浏览型号FSTUD16211MTDX的Datasheet PDF文件第6页浏览型号FSTUD16211MTDX的Datasheet PDF文件第7页 
June 2000  
Revised August 2001  
FSTUD16211  
24-Bit Bus Switch with −2V Undershoot Protection  
and Level Shifting  
General Description  
Features  
■ Undershoot hardened to −2V (A and B Ports)  
The Fairchild Switch FSTUD16211 provides 24-bits of  
high-speed CMOS TTL-compatible bus switching. The low  
on resistance of the switch allows inputs to be connected to  
outputs without adding propagation delay or generating  
additional ground bounce noise. A diode to VCC has been  
■ Voltage level shifting  
■ 4Ω switch connection between two ports  
■ Minimal propagation delay through the switch  
■ Low lCC  
integrated into the circuit to allow for level shifting between  
5V inputs and 3.3V outputs.  
■ Zero bounce in flow-through mode  
The device is organized as a 12-bit or 24-bit bus switch.  
When OE1 is LOW, the switch is ON and Port 1A is con-  
■ Control inputs compatible with TTL level  
■ See Applications Note AN-5008 for details  
nected to Port 1B. When OE2 is LOW, Port 2A is connected  
to Port 2B. When OE1/2 is HIGH, a high impedance state  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA) (Preliminary)  
exists between the A and B Ports. The A and B Ports have  
“undershoot hardened” circuit protection to support an  
extended range to 2.0V below ground. Fairchild’s inte-  
grated Undershoot Hardened Circuit (UHC  
) senses  
undershoot at the I/O’s, and responds by preventing volt-  
age differentials from developing and turning on the switch.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
FSTUD16211GX  
(Note 1)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
FSTUD16211MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Note 1: BGA package available in Tape and Reel only.  
Logic Diagram  
UHC is a trademark of Fairchild Semiconductor Corporation.  
© 2001 Fairchild Semiconductor Corporation  
DS500390  
www.fairchildsemi.com  
12345678

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