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FSTD16861MTD PDF预览

FSTD16861MTD

更新时间: 2024-09-17 23:16:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 开关逻辑集成电路光电二极管驱动
页数 文件大小 规格书
5页 167K
描述
20-Bit Bus Switch with Level Shifting

FSTD16861MTD 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.24
系列:CBT/FST/QS/5C/BJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:12.5 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:2
位数:10功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):0.25 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mmBase Number Matches:1

FSTD16861MTD 数据手册

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May 2001  
Revised May 2001  
FSTD16861  
20-Bit Bus Switch with Level Shifting  
General Description  
Features  
The Fairchild Switch FSTD16861 provides 20-bits of high-  
speed CMOS TTL-compatible bus switching. The low On  
Resistance of the switch allows inputs to be connected to  
outputs without adding propagation delay or generating  
additional ground bounce noise. A diode to VCC has been  
4switch connection between two ports.  
Minimal propagation delay through the switch.  
Low lCC  
.
Zero bounce in flow-through mode.  
Control inputs compatible with TTL level.  
integrated into the circuit to allow for level shifting between  
5V inputs and 3.3V outputs.  
TruTranslation voltage translation from 5.0V inputs to  
3.3V outputs  
The device is organized as a 10-bit or 20-bit bus switch.  
When OE1 is LOW, the switch is ON and Port 1A is con-  
nected to Port 1B. When OE2 is LOW, Port 2A is connected  
to Port 2B. When OEX is HIGH, a high impedance state  
exists between the A and B Ports.  
Ordering Code:  
Order Number Package Number  
Package Description  
FSTD16861MTD  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Truth Table  
Inputs  
Inputs/Outputs  
OE1  
OE2  
1A, 1B  
2A, 2B  
2A = 2B  
Z
Pin Descriptions  
L
L
L
H
L
1A = 1B  
1A = 1B  
Pin Name  
Description  
H
H
Z
Z
2A = 2B  
Z
OE1, OE2  
1An, 2An  
1Bn, 2Bn  
Bus Switch Enables  
Bus A  
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
Z = High Impedance  
Bus B  
TruTranslation is trademark of Fairchild Semiconductor Corporation.  
© 2001 Fairchild Semiconductor Corporation  
DS500421  
www.fairchildsemi.com  

FSTD16861MTD 替代型号

型号 品牌 替代类型 描述 数据表
PI5C16861AEX PERICOM

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