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FSTD162861MTD PDF预览

FSTD162861MTD

更新时间: 2024-09-17 23:16:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器开关逻辑集成电路光电二极管
页数 文件大小 规格书
6页 176K
描述
20-Bit Bus Switch with Level Shifting and 25з Series Resistors in Outputs Preliminary

FSTD162861MTD 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:6.10 MM, MO-153, TSSOP-48针数:48
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:N系列:CBT/FST/QS/5C/B
JESD-30 代码:R-PDSO-G48长度:12.5 mm
逻辑集成电路类型:BUS DRIVER位数:10
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:5 V传播延迟(tpd):1.25 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmBase Number Matches:1

FSTD162861MTD 数据手册

 浏览型号FSTD162861MTD的Datasheet PDF文件第2页浏览型号FSTD162861MTD的Datasheet PDF文件第3页浏览型号FSTD162861MTD的Datasheet PDF文件第4页浏览型号FSTD162861MTD的Datasheet PDF文件第5页浏览型号FSTD162861MTD的Datasheet PDF文件第6页 
Preliminary  
June 2001  
Revised June 2001  
FSTD162861  
20-Bit Bus Switch with Level Shifting  
and 25Series Resistors in Outputs (Preliminary)  
General Description  
Features  
25switch connection between two ports  
Minimal propagation delay through the switch  
Low lCC  
The Fairchild Switch FSTD162861 provides 20-bits of high-  
speed CMOS TTL-compatible bus switching. The low On  
Resistance of the switch allows inputs to be connected to  
outputs without adding propagation delay or generating  
additional ground bounce noise. A diode to VCC has been  
Zero bounce in flow-through mode  
Control inputs compatible with TTL level  
integrated into the circuit to allow for level shifting between  
5V inputs and 3.3V outputs.  
TruTranslation voltage translation from 5.0V inputs to  
3.3V outputs  
The device is organized as a 10-bit or 20-bit bus switch.  
When OE1 is LOW, the switch is ON and Port 1A is con-  
nected to Port 1B. When OE2 is LOW, Port 2A is connected  
to Port 2B. When OEX is HIGH, a high impedance state  
exists between the A and B Ports. The FSTD162861 has  
equivalent 25series resistors to reduce signal-reflection  
noise, eliminating the need for external terminating resis-  
tors.  
Ordering Code:  
Order Number Package Number  
Package Description  
FSTD162861MTD  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
TruTranslation is a trademark of Fairchild Semiconductor Corporation.  
© 2001 Fairchild Semiconductor Corporation  
DS500063  
www.fairchildsemi.com  

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