Datasheet > FS32R372SAK0MMM

FS32R372SAK0MMM

更新时间： 2024-11-18 15:19:11

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
60页	948K
描述
S32R37 multicore Power Architecture, 240 MHz, ISO 26262, AEC-Q100 - S32R MCUs for Radar applications

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FS32R372SAK0MMM 数据手册

Document Number S32R372

Rev. 4, 08/2018

NXP Semiconductors

Data Sheet: Technical Data

S32R372

S32R372 Data Sheet

Features

• Security

– Cryptographic Security Engine (CSE2)

– Supports censorship and life-cycle management

• Dual issue computation cores: Power Architecture®

e200z7 32-bit CPU

• Timers

• 1.3 MB on-chip code flash memory (FMC flash

memory) with ECC

– Two Periodic Interval Timers (PIT) with 32-bit

counter resolution

• 1 MB on-chip SRAM with ECC

– Two System Timer Module (STM)

– Two Software Watchdog Timers (SWT)

– One eTimer module with 6 channels each

– One FlexPWM module for 12 PWM signals

• RADAR processing

– Signal Processing Toolbox (SPT) for RADAR signal

processing acceleration

– Cross Triggering Engine (CTE) for precise timing

generation and triggering

– MIPICSI2 interface to connect external RADAR RX

ADCs

• Communication interfaces

– Two Serial Peripheral interface (SPI) modules

– One LINFlexD module

– Two inter-IC communication interface (I2C)

modules

– Two FlexCAN modules supporting CAN FD with

configurable buffers

• Memory protection

– Each core memory protection unit provides 24

entries

– Data and instruction bus system memory protection

unit (SMPU) with 16 region descriptors each

– Register protection

• Debug functionality

– 4-pin JTAG interface and Nexus/Aurora interface

for serial high-speed tracing

– e200z7 core: Nexus development interface (NDI)

per IEEE-ISTO 5001-2012 Class 3+

• Clock generation

– 40 MHz external crystal (XOSC)

– 16 MHz Internal oscillator (IRCOSC)

– Dual system PLL with one frequency modulated

phase-locked loop (FMPLL)

• Two analog-to-digital converters (SAR ADC)

– Each ADC supports up to 16 input channels

– Cross Trigger Unit (CTU)

– Low-jitter PLL

• On-chip voltage DC/DC regulator for core supply

generation (VREG)

• Functional safety

– Enables ASIL-B applications

– Fault Collection and Control Unit (FCCU) for fault

collection and fault handling

• Two Temperature Sensors (TSENS)

– Memory Error Management Unit (MEMU) for

memory error management

– Safe eDMA controller

– Self-Test Control Unit (STCU2)

– Error Injection Module (EIM)

– On-chip voltage monitoring

– Clock Monitor Unit (CMU)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...60

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与FS32R372SAK0MMM相关器件

型号	品牌	获取价格	描述	数据表
FS32R372SDK0MMMT	NXP	获取价格	S32R37 multicore Power Architecture, 240 MHz, ISO 26262, AEC-Q100 - S32R MCUs for Radar ap
FS32V232BJN1CUB	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BJN1CUBR	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BJN1VUB	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BJN1VUBR	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BKN1CUB	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BKN1CUBR	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BKN1VUB	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BKN1VUBR	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache
FS32V232BLN1CUB	NXP	获取价格	ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache

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