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FMS72509MTCT PDF预览

FMS72509MTCT

更新时间: 2024-11-20 14:50:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 46K
描述
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-24

FMS72509MTCT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.92输入调节:STANDARD
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:7.8 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.015 A功能数量:1
反相输出次数:端子数量:24
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:0.1 ns传播延迟(tpd):0.1 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.12 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

FMS72509MTCT 数据手册

 浏览型号FMS72509MTCT的Datasheet PDF文件第2页浏览型号FMS72509MTCT的Datasheet PDF文件第3页浏览型号FMS72509MTCT的Datasheet PDF文件第4页浏览型号FMS72509MTCT的Datasheet PDF文件第5页浏览型号FMS72509MTCT的Datasheet PDF文件第6页浏览型号FMS72509MTCT的Datasheet PDF文件第7页 
www.fairchildsemi.com  
FMS72509  
Phase Locked Loop Clock Driver  
Features  
Description  
• PC-133 Spread Spectrum Compliant  
• Frequency Range of 25 to 140 MHz  
• VDD Range of 3.0 to 3.6 Volts  
• Up to 11 outputs  
• Less than 100 pS of Output to Output Skew  
• Less than 90 pS of Cycle to Cycle Jitter  
• Output Enable pin  
• Integrated Damping Resistor  
• Commercial Temperature Range  
• Available in 24 pin TSSOP  
FMS72509 is a zero delay clock buffer designed for high fan  
out applications. It contains 10 outputs. It provides precise  
phase and frequency alignment between incoming clock and  
the output clocks. This makes it ideal for high speed applica-  
tion in the range of 25 to 140 MHz. The Phase Locked Loop  
is capable of tracking incoming clock modulation of up to  
±1% of the clock period. With the exception of FBOUT, the  
output Enable (OE) pin, when pulled low, will force the out-  
puts to logic low.  
Block Diagram  
OE1  
FBOUT  
Q0  
Q1  
Q2  
Q3  
FBIN  
Control  
Logic  
Q4  
Q5  
PLL  
CLKIN  
Q6  
Q7  
Q8  
Q9  
OE2  
REV. 1.0 8/11/00  

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