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FMS6410B_06

更新时间: 2024-11-26 04:18:43
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飞兆/仙童 - FAIRCHILD 驱动
页数 文件大小 规格书
8页 214K
描述
Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer

FMS6410B_06 数据手册

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October 2006  
FMS6410B  
Dual-Channel Video Drivers with Integrated Filters and  
Composite Video Summer  
Features  
Description  
7.1MHz fifth-order Y,C filters with composite summer  
The FMS6410B is a dual Y/C fifth-order Butterworth low-  
pass video filter optimized for minimum overshoot and  
flat group delay. The device also contains a summing cir-  
cuit to generate filtered composite video. In a typical  
application, the Y and C input signals from DACs are AC  
coupled into the filters. Both channels have DC restore  
circuitry to clamp the DC input levels during video sync.  
The Y and C channels use separate feedback clamps.  
The clamp pulse is derived from the Y channel.  
50dB stopband attenuation at 27MHz on Y, C, and CV  
outputs  
Better than 0.1dB flatness to 4.5MHz on Y, C, and CV  
outputs  
No external frequency selection components or clocks  
< 5ns group delay on Y, C, and CV outputs  
AC-coupled inputs  
AC- or DC-coupled outputs  
All outputs are capable of driving 2Vpp, AC or DC cou-  
pled, into either a single or dual video load. A single  
video load consists of a series 75Ω impedance matching  
resistor connected to a terminated 75Ω line. This pre-  
sents a total of 150Ω of loading to the part. A dual load is  
two of these in parallel, which presents a total of 75Ω to  
the part. The gain of the Y, C, and CV signals is 6dB with  
1Vpp input levels. All video channels are clamped during  
sync to establish the appropriate output voltage refer-  
ence levels.  
Capable of PAL frequency selection components or  
clocks  
0.3% differential gain with 0.2° differential phase on  
Y, C, and CV channels  
Integrated DC restore circuitry with low tilt  
Lead-free SOIC-8 package  
Applications  
Cable and satellite set-top boxes  
DVD players  
Personal Video Recorders (PVR)  
Video On Demand (VOD)  
Block Diagrams  
VCC  
7
Sync Strip  
Reference and  
Timing  
YIN  
1
8
6
YOUT  
6dB  
gM  
gM  
250mV  
+
Σ
CVOUT  
+
250mV  
CIN  
4
5
COUT  
6dB  
3
GND  
Figure 1. Block Diagram  
© 2004 Fairchild Semiconductor Corporation  
FMS6410B Rev. 1.0.2  
www.fairchildsemi.com  

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