http://www.fujielectric.com/products/semiconductor/
FUJI POWER MOSFET
FML60N091S2HF
Super J MOS® S2 series
Features
N-Channel enhancement mode power MOSFET
Package and Internal circuit chart
Pb-free lead terminal
RoHS compliant
Drain ⑤
Halogen-free molding compound
MSL:1, Reflow available
⑤
Gate ①
Applications
For switching
④
③
Sub-Source
for gate drive ②
②
①
Source ③,④
DFN8x8
(Out view: see to 7/8 page)
Absolute Maximum Ratings at T =25°C (unless otherwise specified)
C
Parameter
Symbol
Characteristics
Unit
Remarks
V
V
DS
600
600
V
Drain-Source Voltage
DSX
V
A
A
A
V
VGS=-30V
42.3
26.8
125.6
±30
T
C
=25°C Note*1,2
=100°C Note*1,2
Continuous Drain Current
ID
T
C
Pulsed Drain Current
Gate-Source Voltage
I
DP
GS
Note *2
V
Non-Repetitive
Maximum Avalanche Current
I
AS
5.5
A
Note *3
Note *4
Non-Repetitive
Maximum Avalanche Energy
E
AS
964.2
mJ
Maximum MOSFET dv/dt
dvDS/dt
50
42.3
V/ns
A
VDS≤ 600V
T
C
=25°C Note*1,2
=100°C Note*1,2
Continuous
Diode Forward Current
I
I
DR
26.8
A
T
C
Pulsed Diode Forward Current
Peak Diode Recovery dv/dt
Peak Diode Recovery -diDR/dt
DRP
125.6
15
A
Note *2
Note *5
Note *6
dv/dt
V/ns
A/μs
W
-diDR/dt
100
263
TC
=25°C
Maximum Power Dissipation
Ptot
2.78
W
T
a
=25°C
Operating Channel Temperature
Storage Temperature
T
ch
150
°C
°C
T
stg
-55 to +150
Note *1 : Maximum duty cycle D=0.55
Note *2 : Limited by maximum channel temperature.
Note *3 : Tch ≤ 150 °C, See Figure 1 and 2.
Note *4 : Starting Tch = 25 °C, IAS = 3.3 A, L = 162 mH, VDD = 60 V, RG = 50 Ω, See Figure 1 and 2.
EAS limited by maximum channel temperature and avalanche current.
Note *5 : IDR ≤ 37.1 A , -diDR/dt ≤ 100 A/μs, VDS peak ≤ 600 V, Tch ≤ 150 °C.
Note *6 : IDR ≤ 37.1 A , dv/dt ≤ 15 V/ns, VDS peak ≤ 600 V, Tch ≤ 150 °C.
9232
NOVEMBER 2017
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