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FM25C020ULZM8

更新时间: 2024-11-30 23:52:19
品牌 Logo 应用领域
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页数 文件大小 规格书
11页 122K
描述
SPI Serial EEPROM

FM25C020ULZM8 数据手册

 浏览型号FM25C020ULZM8的Datasheet PDF文件第2页浏览型号FM25C020ULZM8的Datasheet PDF文件第3页浏览型号FM25C020ULZM8的Datasheet PDF文件第4页浏览型号FM25C020ULZM8的Datasheet PDF文件第5页浏览型号FM25C020ULZM8的Datasheet PDF文件第6页浏览型号FM25C020ULZM8的Datasheet PDF文件第7页 
April 2001  
FM25C020U  
2K-Bit SPI™ Interface  
Serial CMOS EEPROM  
General Description  
Functions  
The FM25C020U is a 2K (2,048) bit serial interface CMOS  
EEPROM (Electrically Erasable Programmable Read-Only  
Memory). This device fully conforms to the SPI 4-wire protocol  
whichusesChipSelect(/CS), Clock(SCK), Data-in(SI)andData-  
out (SO) pins to synchronously control data transfer between the  
SPI microcontroller and the EEPROM. In addition, the serial  
interface allows a minimal pin count, packaging designed to  
simplify PC board layout requirements and offers the designer a  
variety of low voltage and low power options.  
I SPI MODE 0 interface  
I 2,048 bits organized as 256 x 8  
I Extended 2.7V to 5.5V operating voltage  
I 2.1 MHz operation @ 4.5V - 5.5V  
I Self-timed programming cycle  
I "Programming complete" indicated by STATUS REGISTER  
polling  
I /WP pin and BLOCK WRITE protection  
Features  
This SPI EEPROM family is designed to work with the 68HC11 or  
any other SPI-compatible, high-speed microcontroller and offers  
both hardware (/WP pin) and software ("block write") data protec-  
tion. For example, entering a 2-bit code into the STATUS REGIS-  
TER prevents programming in a selected block of memory and all  
I Sequential read of entire array  
I 4 byte "Page write" mode to minimize total write time per  
byte  
programming can be inhibited by connecting the /WP pin to VSS  
;
allowing the user to protect the entire array or a selected section.  
In addition, SPI devices feature a /HOLD pin, which allows a  
temporary interruption of the datastream into the EEPROM.  
I /WP pin and BLOCK WRITE protection to prevent inadvert-  
ent programming as well as programming ENABLE and  
DISABLE opcodes.  
I /HOLD pin to suspend data transfer  
Fairchild EEPROMs are designed and tested for applications  
requiring high endurance, high reliability, and low power con-  
sumption for a continuously reliable non-volatile solution for all  
markets.  
I Typical 1µA standby current (ISB) for "L" devices and 0.1µA  
standby current for "LZ" devices.  
I Endurance: Up to 1,000,000 data changes  
I Data retention greater than 40 years  
Block Diagram  
/CS  
/HOLD  
SCK  
VCC  
VSS  
Instruction  
Decoder  
Control Logic  
and Clock  
/WP  
Instruction  
SI  
Generators  
Register  
Program  
Enable  
Address  
Counter/  
Register  
High Voltage  
Generator  
and  
Program  
Timer  
VPP  
Decoder  
EEPROM Array  
Read/Write Amps  
Data In/Out Register  
8 Bits  
Data Out  
Buffer  
SO  
Non-Volatile  
Status Register  
SPI™ is a trademark of Motorola Corporation  
1
© 2001 Fairchild Semiconductor Corporation  
FM25C020U  
www.fairchildsemi.com  

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