Datasheet > FLLXT384BEB1

FLLXT384BEB1

更新时间： 2024-11-16 08:41:35

品牌	Logo	应用领域
英特尔 - INTEL		PC
页数	文件大小	规格书
140页	1522K
描述
PCM Transceiver, 1-Func, CMOS, PBGA160, 13 X 13MM, BGA-160

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FLLXT384BEB1 数据手册

Intel^®LXT384 Octal T1/E1/J1 Short-Haul

PCM Transceiver with Jitter Attenuation

(JA)

Datasheet

Product Features

■ Octal T1/E1/J1 Pulse-Code Modulation

(PCM) Transceiver with Jitter Attenuation

for use in both 1.544 Mbps (T1) and 2.048

Mbps (E1) applications

■ 16 fully-independent receiver/transmitters

■ Support for E1 standards:

■ Transmitters

—Power-down mode with fast output

tristate capability

—Transmit waveform shaping meets ITU

G.703 and T1.102 specifications

—Exceeds ETSI ETS 300 166 transmit

return-loss specifications

—Exceeds ETSI ETS 300 166

—Meets ETS 300 233

—Low-impedance transmit drivers,

independent of transmit pattern and

supply-voltage variations

■ Low-power single-rail 3.3-V CMOS power

supply, with 5-V tolerant I/Os

■ Jitter attenuation

—Crystal-less

—Low-current transmit output option that

can reduce power dissipation by up to

15%. By changing the LXT384

Transceiver output transformer ratio

from 1:2 to 1:1.7, the savings occur

whether TVCC is at 5 V or 3.3 V.

130 mW per channel (typical). See

Table 63 “Intel^®LXT384 Transceiver

Power Consumption” on page 104 and

Table 64 “Load³Power Consumption”

on page 105.

—Digital clock recovery PLL

—Referenced to a low frequency 1.544

MHz or 2.048-MHz clock. Normal

operation requires only MCLK. Does

not require a reference clock frequency

higher than the line frequency.

—Can be switched between receive and

transmit path

—Meets ETSI CTR12/13, ITU G.736,

G.742, G.823, and AT&T Pub 62411

■ HDB3, B8ZS, or AMI line encoder/decoder

■ LOS per ITU G.775, T1.231, and ETS 300

—Optimized for Synchronous Optical

NETwork (SONET) and Synchronous

Digital Hierarchy (SDH) applications,

meets ITU G.783 mapping jitter standard

233

■ Diagnostics:

—Can be configured for G.722-compliant,

non-intrusive performance (protected)

monitoring points

—Constant throughput delay

■ Differential receiver architecture

—High margin for noise interference

—Operates at >12 dB of cable attenuation

■ Intel^®Hitless Protection Switching

—Industry-standard P1149.1 JTAG

Boundary Scan test port

■ Intel^®/ Motorola* 8-bit parallel processor

interface or 4 wire serial control interface

■ Hardware and Software control modes

■ Operating temperature -40 °C to 85 °C

■ 160-ball BGA or 144-pin LQFP packages

—Eliminates mechanical relays for

redundancy 1+1 protection applications

—Increases quality of service

Applications

■ SONET/SDH tributary interfaces

■ Digital cross connects

■ Microwave transmission systems

■ M13, E1-E3 MUX

■ Public/private switching trunk line interfaces

Document Number: 248994

Revision Number: 005

Revision Date: November 28, 2005

12 3 4 5 6 7...140

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FLLXT971ABE.A4SE000	INTEL	获取价格	Ethernet Transceiver, 1-Trnsvr, CMOS, PBGA64, PLASTIC, BGA-64
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