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FEP30JP PDF预览

FEP30JP

更新时间: 2024-02-20 08:35:01
品牌 Logo 应用领域
赛灵思 - XILINX /
页数 文件大小 规格书
11页 256K
描述
30.0 Ampere Heatsink Dual Common Cathode Ultra Fast Recovery Half Bridge Rectifiers

FEP30JP 技术参数

是否无铅: 不含铅生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.83
Is Samacsys:NBase Number Matches:1

FEP30JP 数据手册

 浏览型号FEP30JP的Datasheet PDF文件第2页浏览型号FEP30JP的Datasheet PDF文件第3页浏览型号FEP30JP的Datasheet PDF文件第4页浏览型号FEP30JP的Datasheet PDF文件第5页浏览型号FEP30JP的Datasheet PDF文件第6页浏览型号FEP30JP的Datasheet PDF文件第7页 
DDR2-400, 533  
Single Rank, x8 Registered SDRAM DIMMs  
256MB - W1D32M72R8  
512MB - W1D64M72R8  
1GB  
2GB  
- W1D128M72R8  
- W1D256M72R8 (Preliminary*)  
Features:  
Figure 1: Available layouts  
Layout A:  
240-pin Registered ECC DDR2 SDRAM Dual-In-  
Line Memory Module for DDR2-400 and DDR2-533  
JEDEC standard VDD=1.8V (+/- 0.1V) power  
supply  
One rank 256MB, 512MB, 1GB, and 2GB  
Modules are built with 18 x8 DDR2 SDRAM  
devices in a 60-ball FBGA package  
ECC error detection and correction  
Programmable CAS Latency of 3 and 4; Burst  
Length of 4 and 8  
Auto Refresh and Self Refresh Mode  
OCD (Off-Chip Driver Impedance Adjustment) and  
ODT (On-Die Termination)  
SPD (Serial Presence Detect) with EEPROM  
All input/output are SSTL_18 compatible  
All contacts are gold plated  
1.181"  
Layout B:  
1.0"  
Front view of double-sided DIMM (see detail physical dimensions  
at the back)  
Speed Grades:  
Speed Grade  
-5  
-3.75  
Units  
One clock delay for register  
Module Speed Grade  
PC2-3200 PC2-4200  
Speed @ CL3  
Speed @ CL4  
Speed @ CL5  
400  
400  
-
-
MHz  
MHz  
MHz  
533  
533  
Note: See Product ordering for full naming guide  
Description:  
The following specification covers the W1D32M72R8, W1D64M72R8, W1D128M72R8, and W1D256M72R8  
family of Single-Rank Registered ECC DDR2 modules using x8 FBGA SDRAMs. Please reference Figure 1 for  
available layout configurations and the product ordering guide on the final page of this specification for available  
options including speed grade and silicon manufacturer.  
Address Summary Table:  
256MB  
32M x 72  
8k  
512MB  
64M x 72  
8K  
1GB  
128M x 72  
8K  
2GB  
256M x 72  
8K  
Module Configuration  
Refresh  
Device Configuration  
32M x 8  
(9 components)  
A0-A13  
A0-A9  
64M x 8  
(9 components)  
A0-A13  
A0-A9  
128M x 8  
(9 components)  
A0-A14  
A0-A9  
256M x 8  
(9 components)  
A0-A14  
A0-A9  
Row Addressing  
Column Addressing  
Module Rank  
1
1
1
1
*Specifications are for reference purposes only and are subject to change by Wintec without notice.  
DDR2_RDIMM_1 rank_x8_spec  
Rev. 1.0 - December, 04  
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  
2004 Wintec Industries, Inc.  
1

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