10K ECL Logic Buffered Delay 16-Pin Modules
5-Tap: DECL • Single: FECL • Triple: MECL
Electrical Specifications at 25OC
Electrical Specifications at 25OC
Tap Delay Tolerances +/- 5% or 1.5ns (+/- 0.8ns <10ns)
Delay
(ns)
Single
10K P/N
Triple
10K P/N
10K ECL
5 Tap P/N
Tap-to-Tap
(ns)
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
3 ± 0.5
4 ± 0.5
FECL-3
FECL-4
FECL-5
MECL-3
MECL-4
MECL-5
MECL-6
MECL-7
MECL-8
MECL-9
MECL-10
MECL-15
MECL-20
MECL-25
MECL-50
----
DECL-6
2.0
3.0
4.0
5.0
6 ± 0.8
1 ± 0.4
2 ± 0.6
DECL-10
DECL-15
DECL-20
DECL-25
DECL-30
DECL-40
DECL-45
DECL-50
DECL-75
DECL-100
DECL-125
DECL-150
DECL-200
DECL-250
2.0
4.0
6.0
8.0
10 ± 1.0
5 ± 0.5
3.0
6.0
9.0
12.0
16.0
20.0
24.0
32.0
36.0
40.0
60.0
80.0
100.0
120.0
160.0
200.0
15 ± 1.5
3 ± 0.8
6 ± 0.75
7 ± 0.75
8 ± 0.8
FECL-6
4.0
8.0
12.0
15.0
18.0
24.0
27.0
30.0
45.0
60.0
75.0
90.0
120.0
150.0
20 ± 1.5
4 ± 1.0
FECL-7
FECL-8
5.0
10.0
12.0
16.0
18.0
20.0
30.0
40.0
50.0
60.0
80.0
100.0
25 ± 1.5
5 ± 1.0
6.0
30 ± 1.5
6 ± 1.5
9 ± 1.0
FECL-9
8.0
40 ± 2.0
8 ± 2.0
10 ± 1.0
15 ± 1.5
20 ± 1.5
25 ± 1.5
50 ± 2.5
60 ± 3.0
75 ± 3.75
100 ± 5.0
FECL-10
FECL-15
FECL-20
FECL-25
FECL-50
FECL-60
FECL-75
FECL-100
9.0
45 ± 2.25
50 ± 2.5
9 ± 2.0
10.0
15.0
20.0
25.0
30.0
40.0
50.0
10 ± 2.0
15 ± 2.5
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
75 ± 3.75
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
----
----
** This part numbers does not have 5 equal taps.
Specified Tap-to-Tap Delays are referenced to Tap 1.
OPERATING SPECIFICATIONS (10K ECL)
DECL Style Schematic
VEE Supply Voltage .............................................. -5.20 ± 0.25 VDC
Supply Current, IEE , DECL.......................... 60 mA typ., 75 mA max.
Supply Current, IEE , FECL .......................... 40 mA typ., 65 mA max.
Supply Current, IEE , MECL ....................... 85 mA typ., 105 mA max.
Vcc Tap1 Tap3 Tap5
15
14
13
16
Logic “1” Input:
VIH ................................................ -0.98 V min.
IIH .................................................. 265 µA max.
VIL ................................................. -1.63 V max.
IIL .................................................. 0.5 mA max.
Logic “0” Input:
V
V
T
OH Logic “1” Voltage Out .............................................. -0.96 V min.
OL Logic “0” Voltage Out .............................................. -1.65V max.
RO Output Rise Time .................................................. < 3.00 ns typ.
1
3
4
5
8
Vcc
Tap2 Tap4
Vee
IN
Input Pulse Width, PWI (DECL,FECL)......... 40% of total delay, min.
Input Pulse Width, PWI (MECL) ................ 100% of total delay, min.
Operating Temperature Range ................................... -30O to +85OC
Storage Temperature Range..................................... -65O to +150OC
FECL Style Schematic
Vcc OUT
OUT
9
16
15
TEST CONDITIONS
(Measurements made at 25OC)
EE SupplyVoltage ................................................................. -5.20VDC
V
Input Pulse Voltage ....................................................... -.80V to -1.80V
Input Pulse Rise Time ......................................................... 3.00ns max.
Input Pulse Period ....................................................... 4.0 x Total Delay
InputPulseDuty Cycle.................................................................... 50%
Outputs terminated through 100 Ω to -2.00 Vdc.
1
4
8
Vcc
Vee
IN
Dimensions in Inches (mm) -- Unused Leads Removed Per Schematic
.810
(20.57)
MAX.
.400
(10.16)
MAX.
MECL Style Schematic
Vcc OUT OUT OUT
3
1
2
15
14
13
16
.260
.300
(6.60)
(7.62)
TYP. MAX.
.120
(3.05)
MIN.
.010
(0.25)
TYP.
8
1
5
6
7
.300
(7.62)
Vcc
Vee
3
IN
IN
IN
1
2
.050
(1.27)
TYP.
.020
(0.51)
TYP.
.100
(2.54)
TYP.
Also Available in 10KH ECL Versions: DECLH, FECLH & MECLH Series
www.rhombus-ind.com
sales@rhombus-ind.com
TEL: (714) 898-0960
FAX: (714) 896-0971
26
DECL_FM 2001-01
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