DATA SHEET
www.onsemi.com
MOSFET – P-Channel,
Logic Level, POWERTRENCH)
V
R
MAX
I MAX
D
DSS
DS(ON)
−40 V
8.0 mW @ −10 V
−65 A
-40 V, -65 A, 8.0 mW
D
FDWS9509L-F085
Features
G
• Typ R
• Typ Q
= 6.3 mW at V = −10 V; I = −65 A
GS D
DS(on)
= 48 nC at V = −10 V; I = −65 A
g(tot)
GS
D
S
• UIS Capability
P−Channel MOSFET
• Wettable Flanks for Automatic Optical Inspection (AOI)
• AEC−Q101 Qualified and PPAP Capable
Bottom
Top
D
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
D
D
D
Compliant
G
Applications
S
S
S
Pin 1
• Automotive Engine Control
• PowerTrain Management
• Solenoid and Motor Drivers
• Electronic Steering
• Integrated Starter/Alternator
• Distributed Power Architectures and VRM
• Primary Switch for 12 V Systems
DFNW8
CASE 507AU
MARKING DIAGRAM
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
ON
AYWWWL
FDWS
9509L
Parameter
Drain−to−Source Voltage
Symbol
Value
−40
16
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
V
Continuous Drain Current
GS
T
T
= 25°C
= 25°C
I
D
−65
A
C
(V = 10 V) (Note 1)
A
Y
= Assembly Location
= Year
Pulsed Drain Current
See
Figure 4
C
WW
WL
= Work Week
= Assembly Lot
Single Pulse Avalanche Energy (Note 2)
Power Dissipation
E
84
mJ
W
AS
FDWS9509L = Specific Device Code
P
107
0.71
D
Derate above 25°C
W/°C
°C
ORDERING INFORMATION
Operating and Storage Temperature
T , T
−55 to
+175
J
STG
†
Device
Package
Shipping
Thermal Resistance (Junction−to−Case)
R
1.4
50
°C/W
°C/W
DFNW8
(Power 56)
(Pb−Free)
q
JC
JA
FDWS9509L−F085
3000 /
Tape & Reel
Maximum Thermal Resistance
(Junction−to−Ambient) (Note 3)
R
q
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Current is limited by wirebond configuration.
2. Starting Tj = 25°C, L = 50 mH, I = 56 A, V = −40 V during inductor charging
AS
DD
and V = 0 V during time in avalanche.
DD
3. R
is the sum of the junction−to−case and case−to−ambient thermal
q
JA
resistance where the case thermal reference is defined as the solder
mounting surface of the drain pins. R
is guaranteed by design while R
q
JA
q
JC
is determined by the user’s board design. The maximum rating presented
2
here is based on mounting on a 1 in pad of 2 oz copper.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
October, 2021 − Rev. 2
FDWS9509L−F085/D