April 2007
TM
UniFET
FDP7N50/FDPF7N50
500V N-Channel MOSFET
Features
Description
•
•
•
•
•
•
7A, 500V, RDS(on) = 0.9Ω @VGS = 10 V
Low gate charge ( typical 12.8 nC)
Low Crss ( typical 9 pF)
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies and active power factor
correction.
Fast switching
100% avalanche tested
Improved dv/dt capability
D
G
TO-220F
TO-220
FDP Series
G D
S
G
D S
FDPF Series
S
Absolute Maximum Ratings
Symbol
Parameter
FDP7N50
FDPF7N50
Unit
VDSS
Drain-Source Voltage
Drain Current
500
V
ID
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
7
4.2
7 *
4.2 *
A
A
(Note 1)
(Note 2)
IDM
Drain Current
- Pulsed
28
28 *
A
V
VGSS
EAS
IAR
Gate-Source voltage
±30
270
7
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
(Note 1)
(Note 1)
(Note 3)
EAR
dv/dt
PD
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
8.9
4.5
mJ
V/ns
Power Dissipation
(TC = 25°C)
- Derate above 25°C
89
0.71
31.3
0.25
W
W/°C
TJ, TSTG
TL
Operating and Storage Temperature Range
-55 to +150
300
°C
Maximum Lead Temperature for Soldering Purpose,
1/8” from Case for 5 Seconds
°C
* Drain current limited by maximum junction temperature.
Thermal Characteristics
Symbol
Parameter
FDP7N50
FDPF7N50
Unit
°C/W
°C/W
RθJC
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink Typ.
Thermal Resistance, Junction-to-Ambient
1.4
0.5
4.0
--
RθCS
RθJA
62.5
62.5
°C/W
©2007 Fairchild Semiconductor Corporation
FDP7N50/FDPF7N50 REV. B
1
www.fairchildsemi.com