December 2011
FDMS3624S
PowerTrench® Power Stage
25V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17.5 A
Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 16 A
Q2: N-Channel
Max rDS(on) = 1.8 mΩ at VGS = 10 V, ID = 30 A
Max rDS(on) = 2.2 mΩ at VGS = 4.5 V, ID = 27 A
Applications
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
Computing
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
Communications
General Purpose Point of Load
Notebook VCORE
RoHS Compliant
G1
Pin 1
D1
D1
D1
D1
Pin 1
PHASE
(S1/D2)
G2
S2
S2
S2
Bottom
Top
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Q1
25
Q2
25
Units
Drain to Source Voltage
Gate to Source Voltage
V
V
(Note 4)
TC = 25 °C
TA = 25 °C
±12
±12
Drain Current
-Continuous (Package limited)
-Continuous
30
60
ID
17.51a
70
301b
120
86
2.51b
1.01d
A
-Pulsed
EAS
Single Pulse Avalanche Energy
(Note 3)
TA = 25 °C
TA = 25 °C
29
mJ
W
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
2.21a
1.01c
PD
TJ, TSTG
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
571a
1251c
3.0
501b
1201d
2.2
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
08OD
07OD
FDMS3624S
Power 56
12 mm
3000 units
©2011 Fairchild Semiconductor Corporation
FDMS3624S Rev.C2
1
www.fairchildsemi.com