Application Tips for the ADS1212/13
last revision : 12/23/97
1. Data Sheet Clarification (PDS-1360B) - Resetting the ADS1212/13 (Slave Mode only),
Figure 27 (pg. 30) - This is a serial reset function for the A/D converter. The data sheet shows the time
sequence of a signal through SCLK which resets the A/D converter into its default condition. A
successful reset will give a 850Hz frequency output on the /DRDY pin (assuming a 10MHz clock at
Xin). The data sheet specifies the time sequence of T1, T2, T1, T2, T3, T2, T4 in Figure 27. The first
parameter, T1 should be T3. The correct sequence is T3, T2, T1, T2, T3, T2, T4.
2. Data Sheet Clarification (PDS-1360B) - Decimation Ratio Calculations (pg. 11) - In the
“DIGITAL FILTER” section of the data sheet there is a formula that is used to determine the correct
Decimation Ratio for a desired data rate. This formula is incorrect. It should be:
fDATA = (fXIN * Turbo Mode) / (128 * [Decimation Ratio +1])
which is equivalent to:
Decimation Ratio = ([fXIN * Turbo Mode] / [128 * fDATA ]) – 1
3. Data Sheet Clarification (PDS-1360B) - Calculating Effective Resolution in Bits vs. Effective
Resolution in Vrms with PGA gains greater than one (pg. 10) - The formulas for the conversion from
bits to Vrms on page 10 of the data sheet assume a PGA gain of one. These formulas can be used for
all PGA settings by changing the constant value of “10V” (in the numerator of both equations) into a
value of “10V / PGA”. To clarify these formulas, Effective Resolution is Bits is a number that refers
to the digital output of the A/D converter. Effective Resolution in Vrms is a voltage and is referred to
the input of the A/D converter. The second to last paragraph of page 10 is incorrect and should be
ignored.
4. Data Sheet Clarification (PDS-1360B) - Continuous Read Mode (pg. 29) : Add this text to
the last paragraph of this section - “Note that once /CS has been taken HIGH, the Continuous Read
Mode will be enabled (but not entered) and can never be disabled. The mode is actually entered and
exited as described previously.”
5. Data Sheet Clarification (PDS-1360B) - Application Circuits, Figure 43 and Figure 44 (pg.
38 and 39) - Pin 6 in the diagram is correctly labeled “AGND”, however, the connection to that pin
“DVDD” is incorrect. This pin should be connected to “AGND”.
6. Data Sheet Clarification (PDS-1360B) - Flowchart for Writing and Reading Register Data,
Slave Mode, Figure 26 (pg. 28) - In the right most flow chart, 5th box down (or second real looking
box), actually reads “External device generates 8 serial clock cycles and receives instruction register data
via SDIO” should read “… and TRANSMITS instruction register data via SDIO”.
7. Data Sheet Clarification (PDS-1360B) - CMR test conditions (pg. 2) - The common-mode
rejection test is performed with a 100mV differential input.
8. Data Sheet Clarification (PDS-1360B) - Organization of the Command Register and Default
Status, Table X. (pg. 19) - The default data rate in Byte 0 is shown to be 850Hz. This in incorrect. If
the Xin clock frequency is 1MHz, the default data rate of the A/D converter at power up will be 340Hz.
9. Data Sheet Clarification (PDS-1360B) - Using Resonators with the ADS1212 and ADS1213,
Pin Definitions (pgs. 4, 5 and 6) - These table imply that a resonator type clock will provide an
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