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74F191SC PDF预览

74F191SC

更新时间: 2024-02-13 16:14:34
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器时钟
页数 文件大小 规格书
7页 80K
描述
Up/Down Binary Counter with Preset and Ripple Clock

74F191SC 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.28Is Samacsys:N
其他特性:TCO OUTPUT计数方向:BIDIRECTIONAL
系列:F/FASTJESD-30 代码:R-PDIP-T16
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):12 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子位置:DUAL
触发器类型:POSITIVE EDGE最小 fmax:125 MHz
Base Number Matches:1

74F191SC 数据手册

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April 1988  
Revised July 1999  
74F191  
Up/Down Binary Counter with Preset and Ripple Clock  
General Description  
Features  
The 74F191 is a reversible modulo-16 binary counter fea-  
turing synchronous counting and asynchronous presetting.  
The preset feature allows the 74F191 to be used in pro-  
grammable dividers. The Count Enable input, the Terminal  
Count output and Ripple Clock output make possible a  
variety of methods of implementing multistage counters. In  
the counting modes, state changes are initiated by the ris-  
ing edge of the clock.  
High-Speed—125 MHz typical count frequency  
Synchronous counting  
Asynchronous parallel load  
Cascadable  
Ordering Code:  
Order Number Package Number  
Package Description  
74F191SC  
74F191SJ  
74F191PC  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009495  
www.fairchildsemi.com  

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