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74ACT1284MSA PDF预览

74ACT1284MSA

更新时间: 2024-01-15 00:28:52
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
7页 229K
描述
IEEE 1284 Transceiver

74ACT1284MSA 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.66差分输出:NO
驱动器位数:4输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:IEEE 1284
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm功能数量:4
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified最大接收延迟:8.5 ns
接收器位数:7座面最大高度:1.2 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:8.5 ns
宽度:4.4 mmBase Number Matches:1

74ACT1284MSA 数据手册

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June 1996  
Revised November 1999  
74ACT1284  
IEEE 1284 Transceiver  
General Description  
Features  
The 74ACT1284 contains four non-inverting bidirectional  
buffers and three non-inverting buffers with open Drain out-  
puts and high drive capability on the B Ports. It is intended  
to provide a standard signaling method for a bi-direction  
parallel peripheral in an Extended Capabilities Port mode  
(ECP).  
TTL-compatible inputs  
A Ports have standard 4 mA totem pole outputs  
Typical input hysteresis of 0.5V  
B Port high drive source/sink capability of 14 mA  
Bidirectional non-inverting buffers  
Supports IEEE P1284 Level 1 and Level 2 signaling  
standards for bidirectional parallel communications  
between personal computers and printing peripherals  
The HD (active HIGH) input pin enables the B Ports to  
switch from open Drain to a high drive totem pole output,  
capable of sourcing 14 mA on all seven buffers. The DIR  
input determines the direction of data flow on the bidirec-  
tional buffers. DIR (active HIGH) enables data flow from A  
Ports to B Ports. DIR (active LOW) enables data flow from  
B Ports to A Ports.  
B Port outputs in High Impedance mode during power  
down  
Guaranteed 4000V minimum ESD protection  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACT1284SC  
74ACT1284MSA  
74ACT1284MTC  
M20B  
MSA20  
MTC20  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
HD  
High Drive Enable input (Active HIGH)  
Direction Control Input  
Side A Inputs or Outputs  
Side B Inputs or Outputs  
Side A Inputs  
DIR  
A
B
A
1 - A4  
1 - B4  
5 - A7  
B5 - B7  
Side B Outputs  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS011683  
www.fairchildsemi.com  

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